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MB9B410R series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf412n/r, mb9bf414n/r, mb9bf415n/r, mb9bf416n/r data sheet (full production) publication number mb9b410 r - ds706 - 00026 revision 3.0 issue date march 11, 2015 confidential notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document ar e not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. d a t a s h e e t MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential notice on data sheet designations spansion inc. issues data sheets with advance information or preliminary designa tions to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they ha ve the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates tha t spansion inc. is developing one or more specific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spans ion inc. therefore places the following conditions upon advance information content: this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice. preliminary the preliminary designation indicates that the product development has progressed such tha t a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production i s achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under consideration. spansion places the following conditions upon preliminary content: this document stat es the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the man ufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. combination some data sheets contain a combination of products with differ ent designations (advance information, preliminary, or full production). this type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc charact eristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time s uch that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed opt ion, temperature range, package type, or vio range. changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. spansion inc. applies the following conditions to documents in this category: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. questions regarding these document designations may be directed to your local sales office. MB9B410R series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf412n/r, mb9bf414n/r, mb9bf415n/r, mb9bf416n/r data sheet (full production) publication num ber MB9B410R - ds706 - 00026 revision 3.0 issue date march 11, 2015 confidential this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. d eems the p roducts to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specif ication corrections, or modifications to the valid combinations offered may occur. ? d escription the mb9b 4 10 r series are a highly integrated 32 - bit microcontrollers dedicated for embedded controllers with high - performance and competitive cost. th ese s eries are based on t he arm cortex - m3 processor with on - chip flash memory and sram , and has peripheral functions such as motor co ntrol timers , adcs and communication interfaces ( can , uart , c sio , i 2 c , lin). the products which are described in this data sheet are placed into type 4 product categories in fm3 family p eripheral m anual . note : arm and cortex are the registered trademarks of arm limited in the eu and other countries. d a t a s h e e t 2 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? f eatures ? 32 - bit arm cortex - m3 core ? processor version : r2p1 ? up to 144mhz frequency operation ? memory protection unit (mpu) : improves the reliability of an embedded system ? integrated nested vectored interrupt co ntroller (nvic) : 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick) : system timer for os task management ? on - chip memories [flash memory] these series are based on two independent on - chip flash memori es . ? mainflash ? up to 512 k byte ? built - in flash accelerator system with 16 kbyte trace buffer memory ? the read access to flash memory can be achieved without wait cycle up to operation frequency of 72mhz. even at the operation frequency more than 72 mhz , an equivalent access to flash memory can be obtained by flash accelerator system. ? security function for code protection ? workflash ? 32 kbyte ? read cycle ? 4 wait - cycle : the operation frequency more than 72 mhz ? 2 wait - cycle : the operation frequency more than 40 mhz , and to 72 mhz ? 0 wait - cycle : the operation frequency to 40 mhz ? security function is shared with code protection [sram] this series contain a total of up to 64 kbyte on - chip sram. this is composed of two independent sram (sram0 , sram1). sram0 is con nected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0 : up to 32 kbyte ? sram1 : up to 32 kbyte ? external bus interface ? supports sram , nor and nand flash device ? up to 8 chip selects ? 8 - /16 - bit data width ? up to 25 - bit add ress bit ? maximum area size : up to 2 56 mbytes ? supports address/data multiplex ? supports external rdy input d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 3 confidential ? can interface (max two channels) ? compatible with can specification 2.0a/b ? maximum transfer rate : 1 mbps ? built - in 32 message buffer ? mult i - function s erial i nterface (max eight channels ) ? 4 channels with 16 steps9 - bit fifo (ch.4 to ch.7) , 4 channels without fifo (ch.0 to ch.3) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c [uart] ? full - duplex double buffe r ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control : automatically control the tran smission by cts/rts (only ch.4) ? various error detect functions available (p arity errors , framing errors , and overrun errors) [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detect function available [lin] ? lin protocol rev.2.1 supported ? full - duplex double buffer ? master/slave mode supported ? lin break field generate (can be changed 13 to 16 - bit length) ? lin break delimiter generate (can be changed 1 to 4 - bit length) ? various error detect functions available (parity errors , framing errors , and overrun errors) [i 2 c] standard - mode (max 100 kbps) / fas t - mode (max 400 k bps) supported ? dma controller ( eight channels) dma controller has an independent bus for cpu , so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or requ est from the built - in peripherals ? transfer address area : 32 - bit (4 gbyte) ? transfer mode : block transfer/burst transfer/demand transfer ? transfer data type : byte/half - word/word ? transfer block count : 1 to 16 ? number of transfers : 1 to 65536 ? a/d converter (ma x 16 channels) [ 12 - bit a/d converter ] ? successive approximation register type ? built - in 3 unit ? conversion time : 1.0 s @ 5 v ? priority conversion available (priority at 2 levels) ? scanning conversion mode ? built - in fifo for conversion data storage (for scan con version : 16steps , for priority conversion : 4steps) d a t a s h e e t 4 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? base timer (max eight channels) operation mode is selectable from the followings for each channel . ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer ? general purpose i/o po rt this series can use its pins as general purpose i/o ports when they are not used for external bus or peripherals. moreover , the port relocate function is built in . it can set which i/o port the peripheral function can be allocated. ? capable of pull - up c ontrol per pin ? capable of reading pin level directly ? built - in the port relocate function ? up 103 fast general purpose i/o ports@ 120 pin package ? some pin is 5v tolerant i/o. s ee " ? p in d escription " to confirm the corresponding pins. ? multi - function t imer (ma x three unit s ) the multi - function timer is composed of the following blocks. ? 16 - bit free - run timer 3ch . /unit ? input capture 4ch . /unit ? output compare 6ch . /unit ? a/d activati on compare 3ch . /unit ? waveform generator 3ch . /unit ? 16 - bit ppg timer 3ch . /un it the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function ? re al - time c lock (rtc) the real - time clock can count year/month/day/hour/minute/second/a day of the week from 01 to 99. ? interrupt function with specifying date and time (year/month/day/hour/minute/second/a day of the week.) is available. this function is also available by specifying only year , month , day , hour or minute. ? timer interrupt function after set time or each set time . ? capable of rewriting the time with continuing the time count. ? leap year automatic count is available. ? quadrature position/ revolution counter (qprc) ( max three channels ) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover , it is possible to use up/down counter. ? the detection edge of the three external event input pins ain , b in and zin is configurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 5 confidential ? dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the f ollowings for each channel . ? free - running ? periodic (=reload) ? one - shot ? watch counter the watch counter is used for wake up from power consumption mode. interval timer : up to 64 s (max) @ sub clock : 32.768 khz ? external interrupt controller unit ? up to 16 ex ternal interrupt input pin ? include one non - maskable interrupt (nmi) ? watchdog t imer ( two channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs , a " hardware " watchdog and a " software " watchdog. " hardware " watchdog timer is clocked by low - speed internal cr oscillator. therefore , " hardware" watchdog is active in any power consumption mode except s top mode . ? crc (cyclic redundancy check) accelerator the crc accelerator hel ps a verify data transmission or storage integrity. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial : 0x1021 ? ieee - 802.3 crc32 generator polynomial : 0x04c11db7 ? clock and reset [clocks] five clock sources (2 external oscilla tor s , 2 internal cr oscillator , and main pll) that are dynamically selectable. ? main clock : 4 mhz to 48 mhz ? sub clock : 32.768 khz ? high - speed internal cr clock : 4 mhz ? low - speed internal cr clock : 100 khz ? main pll clock [resets] ? reset requests from ini tx pin ? power on reset ? software reset ? w atchdog timers reset ? l ow - voltage detector reset ? c lock supervisor reset ? clock super visor (csv) clocks generated by internal cr oscillators are used to supervise abnormality of the external clocks. ? external osc clock f ailure (clock stop) is detected , reset is asserted. ? external osc frequency anomaly is detected , interrupt or reset is asserted. d a t a s h e e t 6 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? low - voltage detector (lvd) this series include 2 - stage monitoring of voltage on the vcc pins . when the voltage falls below the voltage has been set , low - voltage detector generates an interrupt or reset. ? lvd1 : error reporting via interrupt ? lvd2 : auto - reset operation ? low - power c onsumption m ode three power consumption modes supported. ? s leep ? t imer ? s top ? debug ? serial wire jtag debug p ort (swj - dp) ? embedded trace macrocells (etm) provide comprehensive debug and trace facilities. ? power supply wide range voltage : vcc = 2.7 v to 5.5 v d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 7 confidential ? p roduct l ineup ? memory size product name mb9bf 4 12n/r mb9bf 4 14n/r mb9bf 4 15n/r mb9bf 4 16r mainflash 128 k byte 256 kbyte 384 kbyte 512 kbyte workflash 32 kbyte 32 kbyte 32 kbyte 32 kbyte on - chip ram 16 kbyte 32 kbyte 48 kbyte 64 kbyte sram0 8 kbyte 16 kbyte 24 kbyte 32 kbyte sram1 8 kbyte 16 kbyte 24 kbyte 32 kbyte d a t a s h e e t 8 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? function product name mb9bf 4 12n mb9bf 4 14n mb9bf 4 15n mb9bf 4 16n mb9bf 4 12r mb9bf 4 14r mb9bf 4 15r mb9bf 4 16r pin count 1 00 /112 1 20 cpu cortex - m3 freq. 144 mhz power supply voltage range vcc : 2.7 v to 5.5 v can interface 2 ch . (max) dmac 8ch . external bus interface addr : 25 - bit (max) r/wdata : 8 - /16 - bit (max) cs : 8 (max) support : sram , nor flash addr : 25 - bit (max) r/wdata : 8 - /16 - bit (max) cs : 8 (max) support : sram , nor & nand flash mf serial interface (uart/csio/lin/i 2 c) 8ch . (max) ch.4 to ch.7: fifo (16 steps 9 - bit) ch.0 to ch.3: no fifo b ase timer (pwc/ reload timer/pwm/ppg) 8 ch . (max) mf - timer a/d activation compare 3 ch. 3 units (max) input capture 4 ch. free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 3ch . (max) dual timer 1 unit real - time c lock 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 16 pins (max) + nmi 1 i/o ports 83 pins (max) 103 pins (max) 12 - bit a/d converter 16 ch. (3 units) csv (clock super visor) yes lvd (low - vo ltage detector) 2 ch. internal osc high - speed 4 mhz low - speed 100 khz debug function swj - dp/etm note : all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the general i/o port according to your function use. see " ? e lectrical c haracteristics 4.ac characteristics (3)built - in cr oscillation characteristics " for accuracy of built - in cr . d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 9 confidential ? p ackages product name package mb9bf 4 1 2n mb9bf 4 1 4n mb9bf 4 1 5n mb9bf 4 16n mb9bf 4 1 2r mb9bf 4 1 4r mb9bf 4 1 5r mb9bf 4 16r qfp : f pt - 1 00 p - m 36 (0. 6 5 mm pitch) ? - lqfp : f pt - 1 00 p - m23 (0.5 mm pitch) ? - lqfp : fpt - 120p - m37 (0.5 mm pitch) - ? ? bga : bga - 1 12 p - m0 4 (0.8 mm pitch) ? - ? : supported note : see " ? p ackage d imensions " for detailed information on each package. d a t a s h e e t 10 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential ? p in a ssignment ? fpt - 100p - m23 (top view) d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 11 confidential ? fpt - 120p - m37 (top view) d a t a s h e e t 12 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential ? fpt - 100p - m 36 (top view) d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 13 confidential ? bga - 112p - m04 d a t a s h e e t 14 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential ? l ist of p in f unctions ? list of pin numbers the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended p ort function register (epfr) to select the pin . pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 1 b1 1 79 vcc - 2 c1 2 80 p50 e h int00_0 ain0_2 sin3_1 rto10_0 (ppg10_0) m a data0 0 _0 3 c2 3 81 p51 e h int01_0 bin0_2 sot3_1 (sda3_1) rto11_0 (ppg10_0) m a data 0 1 _0 4 b3 4 82 p52 e h int02_0 zin0_2 sck3_1 (scl3_1) rto12_0 (ppg12_0) m a data 0 2 _0 5 d1 5 83 p53 e h si n6_0 tioa1_2 int07_2 rto13_0 (ppg12_0) m a data 0 3 _0 6 d2 6 84 p54 e i sot6_0 (sda6_0) tiob1_2 rto14_0 (ppg14_0) m a data 0 4 _0 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 15 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 7 d3 7 85 p55 e i sck6_0 (scl6_0) adtg_1 rto15_0 (ppg14_0) m a data 0 5 _0 8 d5 8 86 p56 e h int08_2 dtti1x_0 m adata06_0 - - - sin1_0 ( 120pin only) - - 9 - p57 e i sot1_0 (sda1_0) m adata07 _0 - - 10 - p58 e i sck1_0 (scl1_0) ain2_0 m adata08 _0 - - 11 - p59 e h sin7_0 rx1_1 int09_2 bin2_0 m adata09 _0 - - 12 - p5a e i sot7_0 (sda7_0) tx1_1 zin2_0 m ad ata10 _0 - - 13 - p5b e i sck7_0 (scl7_0) madata11 _0 d a t a s h e e t 16 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 9 e1 14 87 p30 e h ain0_0 tiob0_1 int03_2 - madata07_0 ( 100pin only) - - 14 - m adata12_0 ( 120pin only) 10 e2 15 88 p31 e h bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 - madata08_0 ( 100pin only) - - 15 - m adata13_0 ( 120pin only) 11 e3 16 89 p32 e h zin0_0 tiob2_1 sot6_ 1 (sda6_1) int05_2 - madata09_0 ( 100pin only) - - 16 - m adata14_0 ( 120pin only) 12 e4 17 90 p33 e h int04_0 tiob3_1 sin6_1 adtg_6 - madata10_0 ( 100pin only) - - 17 - m adata15_0 ( 120pin only) 13 f1 18 91 p34 e i frck0_0 tiob4_1 tx0_1 - madata11_0 ( 100pin only) - - 18 - m nale_0 ( 120pin only) d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 17 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 14 f2 19 92 p35 e h ic03_0 tiob 5_1 rx0_1 int08_1 - madata12_0 ( 100pin only) - - 19 - m ncle_0 ( 120pin only) 15 f3 20 93 p36 e h ic02_0 sin5_2 int09_1 - madata13_0 ( 100pin only) - - 20 - m nwex_0 ( 120pin only) 16 g1 21 94 p37 e h ic01_0 sot5_2 (sda5_2) int10_1 - madata14_0 ( 100pin only) - - 21 - m nrex_0 ( 120pin only) 17 g2 22 95 p38 e h ic00_0 sck5_2 (scl5_2) int11_1 - madata15_0 ( 100pin only) 18 f4 23 96 p39 e i dtti0x_0 adtg_2 19 g3 24 97 p3a g i rto00_0 (ppg00_0) tioa0_1 rtcco_2 subout_2 - b2 - - vss - d a t a s h e e t 18 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 20 h1 25 98 p3b g i rto01_0 (ppg00_ 0) tioa1_1 21 h2 26 99 p3c g i rto02_0 (ppg02_0) tioa2_1 22 g4 27 100 p3d g i rto03_0 (ppg02_0) tioa3_1 23 h3 28 1 p3e g i rto04_0 (ppg04_0) tioa4_1 24 j2 29 2 p3f g i rto05_0 (ppg04_0) tio a5_1 25 l1 30 3 vss - 26 j1 31 4 vcc - 27 j4 32 5 p40 g h tioa0_0 rto10_1 (ppg10_1) int12_1 28 l5 33 6 p41 g h tioa1_0 rto11_1 (ppg10_1) int13_1 29 k5 34 7 p42 g i tioa2_0 rto12_1 (ppg12_1) 30 j5 35 8 p43 g i tioa3_0 rto13_1 (ppg12_1) adtg_7 - k2 - - vss - - j3 - - vss - - h4 - - vss - d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 19 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 31 h5 36 9 p44 g i tioa4_0 rto14_ 1 (ppg14_1) mad 00 _0 32 l6 37 10 p45 g i tioa5_0 rto15_1 (ppg14_1) mad 01 _0 33 l2 38 11 c - 34 l4 39 12 vss - 35 k1 40 13 vcc - 36 l3 41 14 p46 d m x0a 37 k3 42 15 p47 d n x1a 38 k4 43 16 initx b c 39 k6 44 17 p48 e h dtti1x_1 int14_1 sin3_2 mad 02 _0 40 j6 45 18 p49 e i tiob0_0 ic10_1 ain0_1 sot3_2 (sda3_2) mad 03_0 41 l7 46 19 p4a e i tiob1_0 ic11_1 bin0_1 sck3_2 (scl3_ 2) mad 0 4 _0 42 k7 47 20 p4b e i tiob2_0 ic12_1 zin0_1 mad 05_0 d a t a s h e e t 20 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 43 h6 48 21 p4c i * i tiob3_0 ic13_1 sck7_1 (sc l7_1) ain1_2 mad 06 _0 44 j7 49 22 p4d i* i tiob4_0 frck1_1 sot7_1 (sda7_1) bin1_2 mad 07 _0 45 k8 50 23 p4e i* h tiob5_0 int06_2 sin7_1 zin1_2 mad 08 _0 - - 51 - p70 e i tx0_0 tioa4_2 - - 52 - p71 e h rx0_0 int13_2 tiob4_2 - - 53 - p72 e h sin2_0 int14_2 tioa6_0 - - 54 - p73 e h sot2_0 (sda2_0) int15_2 tiob6_0 - - 55 - p74 e i sck2_0 (scl2_ 0) 46 k9 56 24 pe0 c p md1 47 l8 57 25 md0 p d d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 21 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 48 l9 58 26 pe2 a a x0 49 l10 59 27 pe3 a b x1 50 l11 60 28 vss - 51 k11 61 29 vcc - 52 j11 62 30 p10 f k an00 53 j10 63 31 p11 f l an01 sin1_1 int02_1 rx1_2 frck0_2 mad09 _0 - k10 - - vss - - j9 - - vss - 54 j8 64 32 p12 f k an02 sot1_1 (sda1_1) tx1_2 ic00_2 mad 10 _0 55 h10 65 33 p13 f k an03 sck1_1 (scl1_1) rtcco_1 subout_1 ic01_2 mad 11_0 d a t a s h e e t 22 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 56 h9 66 34 p14 f l an04 sin0_1 int03_1 ic02_2 m ad12 _0 57 h7 67 35 p15 f k an05 sot0_1 (sda0_1) ic03_2 m ad13 _0 58 g10 68 36 p16 f k an06 sck0_1 (scl0_1) m ad14 _0 59 g9 69 37 p17 f l an07 sin2_2 int04_1 m ad15 _0 60 h11 70 38 avcc - 61 f11 71 39 avrh - 62 g11 72 40 avss - 63 g8 73 41 p18 f k an08 sot2_2 (sda2_2) m ad16 _0 64 f10 74 42 p19 f k an09 sck2_2 (scl2_2) m ad17 _0 65 f9 75 43 p1a f l an10 sin4_1 int05_1 ic00_1 m ad18 _0 - h8 - - vss - d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 23 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 66 e11 76 44 p1b f k an11 sot4_1 (sda4_1) ic01_1 m ad19 _0 67 e10 77 45 p1c f k an12 sck4_1 (scl4_1) ic02_1 m ad20 _0 68 f8 78 46 p1d f k an13 cts4_1 ic03_1 m ad21 _0 69 e9 79 47 p1e f k an14 rts4_1 dtti0x_1 m ad22 _0 70 d1 1 80 48 p1f f k an15 adtg_5 frck0_1 m ad23 _0 - - 8 1 - p28 e i tiob6_2 adtg_4 rto05_1 (ppg04_1) - - 82 - p27 e h tioa6_2 int02_2 rto04_1 (ppg04_1) - - 83 - p26 e i sck2_1 (scl2_1) rto03_1 (ppg02_1) d a t a s h e e t 24 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 - - 84 - p25 e i tx1_0 sot2_1 (sda2_1) rto02_1 (ppg02_1) - b10 - - vss - - c9 - - vss - - - 85 - p24 e h rx1 _0 sin2_1 int01_2 rto01_1 (ppg00_1) 7 1 d10 8 6 49 p23 e i sck0_0 (scl0_0) tioa7_1 - - - rto00_1 (ppg00_1) 7 2 e8 8 7 50 p22 e i sot0_0 (sda0_0) tiob7_1 zin1_1 7 3 c11 8 8 51 p21 e h sin0_0 int06_1 bin1_1 7 4 c10 8 9 52 p20 e h int05_0 crout _0 ain1_1 mad24 _0 75 a11 90 53 vss - 76 a10 91 54 vcc - 77 a9 92 55 p00 e e trstx mcsx7 _0 78 b9 93 56 p01 e e tck swclk d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 25 confidential pin no pi n name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 79 b11 94 57 p02 e e tdi mcsx6_0 80 a8 95 58 p03 e e tms swdio 81 b8 96 59 p04 e e tdo swo 82 c8 97 60 p05 e f traced0 t ioa5_2 sin4_2 int00_1 mcsx5 _0 - d8 - - vss - 83 d9 98 61 p06 e f traced1 tiob5_2 sot4_2 (sda4_2) int01_1 ain2_1 mcsx4 _0 84 a7 99 62 p07 e g traced2 adtg_0 sck4_2 (scl4_2 ) bin2_1 mclkout_0 85 b7 100 63 p08 e g traced3 tioa0_2 cts4_2 zin2_1 mcsx3 _0 86 c7 101 64 p09 e g traceclk tiob0_2 rts4_2 rto20_1 (ppg20_1) mcsx2 _0 d a t a s h e e t 26 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 87 d7 102 65 p0a i * h sin4_0 int00_2 frck1_0 frck2_0 rto21_1 (ppg20_1) m csx1_0 88 a6 103 66 p0b i * i sot4_0 (sda4_0) tiob6_1 ic10_0 ic20_0 rto22_1 (ppg22_1) m csx0_0 89 b6 104 67 p0c i * i sck4_0 (scl4_0) tioa6_1 ic11_0 ic21_0 rto23_1 ma le _0 90 c6 105 68 p0d e i rts4_0 tioa3_2 ic12_0 ic 22_0 rto24_1 (ppg24_1) m dqm0 _0 91 a5 106 69 p0e e i cts4_0 tiob3_2 ic13_0 ic23_0 rto25_1 (ppg24_1) m dqm1 _0 - d4 - - vss - - c3 - - vss - d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 27 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 92 b5 107 70 p0f e j nmix crout_1 rtcco_0 subout_0 dtti2x_0 dtti2x_1 - - 108 - p68 g h sck3_0 (scl3_0) tiob7_2 int12_2 ic20_1 rto25_0 (ppg24_0) - - 109 - p67 g i sot3_0 (sda3_0) tioa7_2 ic21_1 rto24_0 (ppg24_0) - - 110 - p66 g h sin3_0 adtg_8 int11_2 ic22_1 rto23_0 (ppg22_0) - - 111 - p65 g i tiob7_0 sck5_1 (scl5_1) ic23_1 rto22_0 (ppg22_0) - - 112 - p64 g h tioa7_0 sot5_1 (sda5_1) int10_2 frck2_1 rto21_0 (ppg20_0) d a t a s h e e t 28 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential pin no pin name i/o circuit type pin state type lqfp - 100 bga - 112 lqfp - 120 qfp - 100 93 d6 113 71 p63 g h int03_0 sin5_1 rx0_2 mwex_0 - - - rto20_0 (ppg20_0) 94 c5 114 72 p62 e i sck5_0 (scl5_0) adtg_3 tx0_2 m oex _0 95 b4 115 73 p61 e i sot5_0 (sda5_0) tiob2_2 96 c4 116 74 p60 i * h sin5_0 tioa2_2 int15_1 mrdy _0 97 a4 117 75 vcc - 98 a3 118 76 p80 h o 99 a2 119 77 p81 h o 100 a1 120 78 vss - * : 5 v tolerant i/o d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 29 confidential ? list of pin functions the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 adc adtg_0 a/d converter external trigger input pin 84 a7 99 62 adtg_1 7 d3 7 85 adtg_2 18 f4 23 96 adtg_3 94 c5 114 72 adtg_4 - - 8 1 - adtg_5 70 d11 80 48 adtg_6 12 e4 17 90 adtg_7 30 j5 35 8 adtg_8 - - 110 - an00 a/d converter analog input pin . anxx describes adc ch.xx . 52 j11 62 30 an01 53 j10 63 31 an02 54 j8 64 32 an03 55 h10 65 33 an04 56 h9 66 34 an05 57 h7 67 35 an06 58 g10 68 36 an07 59 g9 69 37 an08 63 g8 73 41 an09 64 f 10 74 42 an10 65 f9 75 43 an11 66 e11 76 44 an12 67 e10 77 45 an13 68 f8 78 46 an14 69 e9 79 47 an15 70 d11 80 48 base timer 0 tioa0_0 base timer ch.0 tioa pin 27 j4 32 5 tioa0_1 19 g3 24 97 tioa0_2 85 b7 100 63 tiob0_0 base time r ch.0 tiob pin 40 j6 45 18 tiob0_1 9 e1 14 87 tiob0_2 86 c7 101 64 base timer 1 tioa1_0 base timer ch.1 tioa pin 28 l5 33 6 tioa1_1 20 h1 25 98 tioa1_2 5 d1 5 83 tiob1_0 base timer ch.1 tiob pin 41 l7 46 19 tiob1_1 10 e2 15 88 tiob1_2 6 d2 6 84 base timer 2 tioa2_0 base timer ch.2 tioa pin 29 k5 34 7 tioa2_1 21 h2 26 99 tioa2_2 96 c4 116 74 tiob2_0 base timer ch.2 tiob pin 42 k7 47 20 tiob2_1 11 e3 16 89 tiob2_2 95 b4 115 73 d a t a s h e e t 30 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 base timer 3 tioa3_0 base timer ch.3 tioa pin 30 j5 35 8 tioa3_1 22 g4 27 100 tioa3_2 90 c6 105 68 tiob3_0 base timer ch.3 tiob pin 43 h6 48 21 tiob3_1 12 e4 17 90 tiob3_2 91 a5 106 69 base timer 4 tioa4_0 b ase timer ch.4 tioa pin 31 h5 36 9 tioa4_1 23 h3 28 1 tioa4_2 - - 51 - tiob4_0 base timer ch.4 tiob pin 44 j7 49 22 tiob4_1 13 f1 18 91 tiob4_2 - - 52 - base timer 5 tioa5_0 base timer ch.5 tioa pin 32 l6 37 10 tioa5_1 24 j2 29 2 tioa5_ 2 82 c8 97 60 tiob5_0 base timer ch.5 tiob pin 45 k8 50 23 tiob5_1 14 f2 19 92 tiob5_2 83 d9 98 61 base timer 6 tioa6_ 0 base timer ch.6 tioa pin - - 53 - tioa6_1 89 b6 104 67 tioa6_ 2 - - 82 - tiob6_ 0 base timer ch.6 tiob pin - - 54 - ti ob6_1 88 a6 103 66 tiob6_ 2 - - 81 - base timer 7 tioa7_0 base timer ch.7 tioa pin - - 112 - tioa7_1 71 d10 86 49 tioa7_2 - - 109 - tiob7_0 base timer ch.7 tiob pin - - 111 - tiob7_1 72 e8 87 50 tiob7_2 - - 108 - can 0 tx0_0 can interfac e ch.0 tx output pin - - 51 - tx0_1 13 f1 18 91 tx0_2 94 c5 114 72 rx0_0 can interface ch.0 rx output pin - - 52 - rx0_1 14 f2 19 92 rx0_2 93 d6 113 71 can 1 tx1_0 can interface ch.1 tx output pin - - 84 - tx1_1 - - 12 - tx1_2 54 j8 64 32 rx1_0 can interface ch.1 rx output pin - - 85 - rx1_1 - - 11 - rx1_2 53 j10 63 31 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 31 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 debugger swclk serial wire debug interface clock input pin 78 b9 93 56 swdio ser ial wire debug interface data input / output pin 80 a8 95 58 swo serial wire viewer output pin 81 b8 96 59 tck j - tag test clock input pin 78 b9 93 56 tdi j - tag test data input pin 79 b11 94 57 tdo j - tag debug data output pin 81 b8 96 59 tms j - tag test mode state input/output pin 80 a8 95 58 traceclk trace clk output pin of etm 86 c7 101 64 traced0 trace data output pin of etm 82 c8 97 60 traced1 83 d9 98 61 traced2 84 a7 99 62 traced3 85 b7 100 63 trstx j - tag test reset input pin 77 a9 92 55 external bus mad00 _0 external bus interface address bus 31 h5 36 9 mad01 _0 32 l6 37 10 mad02 _0 39 k6 44 17 mad03 _0 40 j6 45 18 mad04 _0 41 l7 46 19 mad05 _0 42 k7 47 20 mad06 _0 43 h6 48 21 mad07 _0 44 j7 49 22 mad08 _0 45 k8 50 23 mad09 _0 53 j10 63 31 mad10 _0 54 j8 64 32 mad11 _0 55 h10 65 33 mad12 _0 56 h9 66 34 mad13 _0 57 h7 67 35 mad14 _0 58 g10 68 36 mad15 _0 59 g9 69 37 mad16 _0 63 g8 73 41 mad17 _0 64 f10 74 42 mad18 _0 65 f9 75 43 mad19 _0 66 e1 1 76 44 mad20 _0 67 e10 77 45 mad21 _0 68 f8 78 46 mad22 _0 69 e9 79 47 mad23 _0 70 d11 80 48 mad24 _0 74 c10 89 52 mcsx0 _0 external bus interface chip select output pin 88 a6 103 66 mcsx1 _0 87 d7 102 65 mcsx2 _0 86 c7 101 64 mcsx3 _0 85 b7 100 63 mcsx4 _0 83 d9 98 61 mcsx5 _0 82 c8 97 60 mcsx6 _0 79 b11 94 57 mcsx7 _0 77 a9 92 55 d a t a s h e e t 32 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 external bus m a data0 _0 external bus interface data bus (address / data mu ltiplex bus) 2 c1 2 80 m a data1 _0 3 c2 3 81 m a data2 _0 4 b3 4 82 m a data3 _0 5 d1 5 83 m a data4 _0 6 d2 6 84 m a data5 _0 7 d3 7 85 m a data6 _0 8 d5 8 86 m a data7 _0 9 e1 9 87 m a data8 _0 10 e2 10 88 m a data9 _0 11 e3 11 89 m a data10 _0 12 e4 12 90 m a data11 _0 13 f1 13 91 m a data12 _0 14 f2 14 92 m a data13 _0 15 f3 15 93 m a data14 _0 16 g1 16 94 m a data15 _0 17 g2 17 95 mdqm0 _0 external bus interface byte mask signal output pin 90 c6 105 68 mdqm1 _0 91 a5 106 69 male_0 external bus in terface address latch enable output signal for multiplex 89 b6 104 67 mrdy_0 external bus interface external rdy input signal 96 c4 116 74 mclkout_0 external bus interface external clock output pin 84 a7 99 62 mnale _0 external bus interface ale signa l to control nand flash output pin - - 18 - mncle _0 external bus interface cle signal to control nand flash output pin - - 19 - mnrex _0 external bus interface read enable signal to control nand flash - - 21 - mnwex _0 external bus interface write enab le signal to control nand flash - - 20 - moex _0 external bus interface read enable signal for sram 94 c5 114 72 mwex _0 external bus interface write enable signal for sram 93 d6 113 71 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 33 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 12 0 qfp - 1 00 external interrupt int00_0 external interrupt request 00 input pin 2 c1 2 80 int00_1 82 c8 97 60 int00_2 87 d7 102 65 int01_0 external interrupt request 01 input pin 3 c2 3 81 int01_1 83 d9 98 61 int01_2 - - 85 - int02_0 externa l interrupt request 02 input pin 4 b3 4 82 int02_1 53 j10 63 31 int02_2 - - 82 - int03_0 external interrupt request 03 input pin 93 d6 113 71 int03_1 56 h9 66 34 int03_2 9 e1 14 87 int04_0 external interrupt request 04 input pin 12 e4 17 90 int04_1 59 g9 69 37 int04_2 10 e2 15 88 int05_0 external interrupt request 05 input pin 74 c10 89 52 int05_1 65 f9 75 43 int05_2 11 e3 16 89 int06_1 external interrupt request 06 input pin 73 c11 88 51 int06_2 45 k8 50 23 int07_2 exte rnal interrupt request 07 input pin 5 d1 5 83 int08_1 external interrupt request 08 input pin 14 f2 19 92 int08_2 8 d5 8 86 int09_1 external interrupt request 09 input pin 15 f3 20 93 int09_2 - - 11 - int10_1 external interrupt request 10 input pin 16 g1 21 94 int10_2 - - 112 - int11_1 external interrupt request 11 input pin 17 g2 22 95 int11_2 - - 110 - int12_1 external interrupt request 1 2 input pin 27 j4 32 5 int12_2 - - 108 - int13_1 external interrupt request 1 3 input pin 28 l5 33 6 int13_2 - - 52 - int14_1 external interrupt request 1 4 input pin 39 k6 44 17 int14_2 - - 53 - int15_1 external interrupt request 1 5 input pin 96 c4 116 74 int15_2 - - 54 - nmix non - maskable interrupt input pin 92 b5 107 70 d a t a s h e e t 34 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential modul e pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 gpio p00 general - purpose i/o port 0 77 a9 92 55 p01 78 b9 93 56 p02 79 b11 94 57 p03 80 a8 95 58 p04 81 b8 96 59 p05 82 c8 97 60 p06 83 d9 98 61 p07 84 a7 99 62 p0 8 85 b7 100 63 p09 86 c7 101 64 p0a 87 d7 102 65 p0b 88 a6 103 66 p0c 89 b6 104 67 p0d 90 c6 105 68 p0e 91 a5 106 69 p0f 92 b5 107 70 p10 general - purpose i/o port 1 52 j11 62 30 p11 53 j10 63 31 p12 54 j8 64 32 p13 55 h10 6 5 33 p14 56 h9 66 34 p15 57 h7 67 35 p16 58 g10 68 36 p17 59 g9 69 37 p18 63 g8 73 41 p19 64 f10 74 42 p1a 65 f9 75 43 p1b 66 e11 76 44 p1c 67 e10 77 45 p1d 68 f8 78 46 p1e 69 e9 79 47 p1f 70 d11 80 48 p20 general - purp ose i/o port 2 74 c10 89 52 p21 73 c11 88 51 p22 72 e8 87 50 p23 71 d10 86 49 p24 - - 85 - p25 - - 84 - p26 - - 83 - p27 - - 82 - p28 - - 81 - d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 35 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 gpio p30 general - purpose i/o port 3 9 e1 14 87 p31 10 e2 15 88 p32 11 e3 16 89 p33 12 e4 17 90 p34 13 f1 18 91 p35 14 f2 19 92 p36 15 f3 20 93 p37 16 g1 21 94 p38 17 g2 22 95 p39 18 f4 23 96 p3a 19 g3 24 97 p3b 20 h1 25 98 p3c 21 h2 26 99 p3d 22 g4 27 100 p3e 23 h3 28 1 p3f 24 j2 29 2 p40 general - purpose i/o port 4 27 j4 32 5 p41 28 l5 33 6 p42 29 k5 34 7 p43 30 j5 35 8 p44 31 h5 36 9 p45 32 l6 37 10 p46 36 l3 41 14 p47 37 k3 42 15 p48 39 k6 44 1 7 p49 40 j6 45 18 p4a 41 l7 46 19 p4b 42 k7 47 20 p4c 43 h6 48 21 p4d 44 j7 49 22 p4e 45 k8 50 23 p50 general - purpose i/o port 5 2 c1 2 80 p51 3 c2 3 81 p52 4 b3 4 82 p53 5 d1 5 83 p54 6 d2 6 84 p55 7 d3 7 85 p56 8 d5 8 86 p57 - - 9 - p58 - - 10 - p59 - - 11 - p5a - - 12 - p5b - - 13 - d a t a s h e e t 36 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 gpio p60 general - purpose i/o port 6 96 c4 116 74 p61 95 b4 115 73 p62 94 c5 114 72 p 63 93 d6 113 71 p64 - - 112 - p65 - - 111 - p66 - - 110 - p67 - - 109 - p68 - - 108 - p70 general - purpose i/o port 7 - - 51 - p71 - - 52 - p72 - - 53 - p73 - - 54 - p74 - - 55 - p80 general - purpose i/o port 8 98 a3 118 76 p81 99 a2 119 77 pe0 general - purpose i/o port e 46 k9 56 24 pe2 48 l9 58 26 pe3 49 l10 59 27 multi - f unction serial 0 sin0_0 multi - function serial interface ch.0 input pin 73 c11 88 51 sin0_1 56 h9 66 34 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 72 e8 87 50 sot0_1 (sda0_1) 57 h7 67 35 sck0_0 (scl0_0) multi - function serial i nterface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as scl0 when it is used in an i 2 c (operation mode 4). 71 d10 86 49 sck0_1 (scl0_1) 58 g10 68 36 multi - f unction serial 1 sin1_0 multi - function serial interface ch.1 input pin - - 8 - sin1_1 53 j10 63 31 sot1_0 (sda1_0) multi - function serial interface ch.1 output pin. this pin operates as sot1 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda1 when it is used in an i 2 c (operation mode 4). - - 9 - sot1_1 (sda1_1) 54 j8 64 32 sck1_0 (scl1_0) multi - function serial interface ch.1 clock i/o pin. this pin operates as sck1 when it is used in a csio (operation modes 4 ) and as scl1 when it is used in an i 2 c (operatio n mode 4). - - 10 - sck1_1 (scl1_1) 55 h10 65 33 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 37 confidential module pin name function pin no. lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction serial 2 sin2_0 multi - function serial interface ch.2 input pin - - 53 - sin2_1 - - 85 - sin2_2 59 g9 6 9 37 sot2_0 (sda2_0) multi - function serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). - - 54 - sot2_1 (sda2_1) - - 84 - s ot2_2 (sda2_2) 63 g8 73 41 sck2_0 (scl2_0) multi - function serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a csio (operation modes 2 ) and as scl2 when it is used in an i 2 c (operation mode 4). - - 55 - sck2_1 (scl2_1) - - 83 - sck2_2 (scl2_2) 64 f10 74 42 multi - f unction serial 3 sin3_0 multi - function serial interface ch.3 input pin - - 110 - sin3_1 2 c1 2 80 sin3_2 39 k6 44 17 sot3_0 (sda3_0) multi - function serial interface ch.3 output pin. this pin operate s as sot3 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda3 when it is used in an i 2 c (operation mode 4). - - 109 - sot3_1 (sda3_1) 3 c2 3 81 sot3_2 (sda3_2) 40 j6 45 18 sck3_0 (scl3_0) multi - function serial interface ch.3 clo ck i/o pin. this pin operates as sck3 when it is used in a csio (operation modes 2 ) and as scl3 when it is used in an i 2 c (operation mode 4). - - 108 - sck3_1 (scl3_1) 4 b3 4 82 sck3_2 (scl3_2) 41 l7 46 19 d a t a s h e e t 38 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential module pin name function pin no lqf p - 100 bga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction serial 4 sin4_0 multi - function serial interface ch.4 input pin 87 d7 102 65 sin4_1 65 f9 75 43 sin4_2 82 c8 97 60 sot4_0 (sda4_0) multi - function serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda4 when it is used in an i 2 c (operation mode 4). 88 a6 103 66 sot4_1 (sda4_1) 66 e11 76 44 sot4_2 (sda4_2) 83 d9 98 61 sck4_0 (scl4_0) multi - function serial interface ch. 4 clock i/o pin. this pin operates as sck4 when it is used in a csio (operation modes 2 ) and as scl4 when it is used in an i 2 c (operation mode 4). 89 b6 104 67 sck4_1 (scl4_1) 67 e10 77 45 sck4_2 (scl4_2) 84 a7 99 62 rts4_0 multi - function serial in terface ch.4 rts output pin 90 c6 105 68 rts4_1 69 e9 79 47 rts4_2 86 c7 101 64 cts4_0 multi - function serial interface ch.4 cts input pin 91 a5 106 69 cts4_1 68 f8 78 46 cts4_2 85 b7 100 63 multi - f unction serial 5 sin5_0 multi - function seri al interface ch.5 input pin 96 c4 116 74 sin5_1 93 d6 113 93 sin5_2 15 f3 20 93 sot5_0 (sda5_0) multi - function serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 95 b4 115 73 sot5_1 (sda5_1) - - 112 - sot5_2 (sda5_2) 16 g1 21 94 sck5_0 (scl5_0) multi - function serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a csio (operation modes 2 ) and as scl5 when it is used in an i 2 c (operation mode 4). 94 c5 114 72 sck5_1 (scl5_1) - - 111 - sck5_2 (scl5_2) 17 g2 22 95 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 39 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction serial 6 sin6_0 multi - functio n serial interface ch.6 input pin 5 d1 5 83 sin6_1 12 e4 17 90 sot6_0 (sda6_0) multi - function serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda6 when it is used in an i 2 c (operation mode 4). 6 d2 6 84 sot6_1 (sda6_1) 11 e3 16 89 sck6_0 (scl6_0) multi - function serial interface ch.6 clock i/o pin. this pin operates as sck6 when it is used in a csio (operation modes 2 ) and as scl6 when it is used in an i 2 c (operation mod e 4). 7 d3 7 85 sck6_1 (scl6_1) 10 e2 15 88 multi - f unction serial 7 sin7_0 multi - function serial interface ch.7 input pin - - 11 - sin7_1 45 k8 50 23 sot7_0 (sda7_0) multi - function serial interface ch.7 output pin. this pin operates as sot7 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda7 when it is used in an i 2 c (operation mode 4). - - 12 - sot7_1 (sda7_1) 44 j7 49 22 sck7_0 (scl7_0) multi - function serial interface ch.7 clock i/o pin. this pin operates as sck7 when it is used in a csio (operation modes 2 ) and as scl7 when it is used in an i 2 c (operation mode 4). - - 13 - sck7_1 (scl7_1) 43 h6 48 21 d a t a s h e e t 40 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction timer 0 dtti0x_0 input signal controlling wave form generator outputs rto00 to rto05 of multi - function timer 0. 18 f4 23 96 dtti0x_1 69 e9 79 47 frck0_0 16 - bit free - run timer ch.0 external clock input pin 13 f1 18 91 frck0_1 70 d11 80 48 frck0_ 2 53 j10 63 31 ic00_0 16 - bit input capture ch.0 input pin of multi - function timer 0 . icxx describes chan n el number. 17 g2 22 95 ic00_1 65 f9 75 43 ic00_ 2 54 j8 64 32 ic01_0 16 g1 21 94 ic01_1 66 e11 76 44 ic01_ 2 55 h10 65 33 ic02_0 15 f3 20 93 ic02_1 67 e10 77 45 ic 02_ 2 56 h9 66 34 ic03_0 14 f2 19 92 ic03_1 68 f8 78 46 ic03_ 2 57 h7 67 35 rto00_0 (ppg00_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output modes. 19 g3 24 97 rto0 0_1 (ppg00_1) - - 86 - rto01_0 (ppg00_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output modes. 20 h1 25 98 rto01_1 (ppg00_1) - - 85 - rto02_0 (ppg02_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output modes. 21 h2 26 99 rto02_1 (ppg02_1) - - 84 - rto03_0 (ppg02_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is us ed in ppg0 output modes. 22 g4 27 100 rto03_1 (ppg02_1) - - 83 - rto04_0 (ppg04_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output modes. 23 h3 28 1 rto04_1 (ppg04_1) - - 82 - rt o05_0 (ppg04_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output modes. 24 j2 29 2 rto05_1 (ppg04_1) - - 81 - d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 41 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction timer 1 dtti1x_0 input signal controlling wave form generator outputs rto10 to rto15 of multi - function timer 1. 8 d5 8 86 dtti1x_1 39 k6 44 17 frck1_0 16 - bit free - run timer ch.1 external clock input pin 87 d7 102 65 frck1_1 44 j 7 49 22 ic10_0 16 - bit input capture ch.1 input pin of multi - function timer 1. icxx describes chan n el number . 88 a6 103 66 ic10_1 40 j6 45 18 ic11_0 89 b6 104 67 ic11_1 41 l7 46 19 ic12_0 90 c6 105 68 ic12_1 42 k7 47 20 ic13_0 91 a5 106 69 ic13_1 43 h6 48 21 rto10_0 (ppg10_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 2 c1 2 80 rto10_1 (ppg10_1) 27 j4 32 5 rto11_0 (ppg10_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 3 c2 3 81 rto11_1 (ppg10_1) 28 l5 33 6 rto12_0 (ppg12_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg12 when it is u sed in ppg1 output modes. 4 b3 4 82 rto12_1 (ppg12_1) 29 k5 34 7 rto13_0 (ppg12_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg12 when it is used in ppg1 output modes. 5 d1 5 83 rto13_1 (ppg12_1) 30 j5 35 8 r to14_0 (ppg14_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 6 d2 6 84 rto14_1 (ppg14_1) 31 h5 36 9 rto15_0 (ppg14_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 7 d3 7 85 rto15_1 (ppg14_1) 32 l6 37 10 d a t a s h e e t 42 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction timer 2 dtti 2 x_0 input signal controlling wave f orm generator outputs rto20 to rto25 of multi - function timer 2. 92 b5 107 70 dtti 2 x_1 92 b5 107 70 frck 2 _0 16 - bit free - run timer ch.2 external clock input pin 87 d7 102 65 frck 2 _1 - - 112 - ic 2 0_0 16 - bit input capture ch.2 input pin of multi - func tion timer 2. icxx describes chan n el number. 88 a6 103 66 ic 2 0_1 - - 108 - ic 2 1_0 89 b6 104 67 ic 2 1_1 - - 109 - ic 2 2_0 90 c6 105 68 ic 2 2_1 - - 110 - ic 2 3_0 91 a5 106 69 ic 2 3_1 - - 111 - rto 2 0_0 (ppg2 0_0) wave form generator output pi n of multi - function timer 2. this pin operates as ppg20 when it is used in ppg2 output modes. - - 113 - rto 2 0_1 (ppg2 0_1) 86 c7 101 64 rto 2 1_0 (ppg 2 0_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg20 when it is us ed in ppg2 output modes. - - 112 - rto 2 1_1 (ppg 2 0_1) 87 d7 102 65 rto 2 2_0 (ppg2 2_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg22 when it is used in ppg2 output modes. - - 111 - rto 2 2_1 (ppg2 2_1) 88 a6 103 66 rto 2 3_0 (ppg2 2_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg22 when it is used in ppg2 output modes. - - 110 - rto 2 3_1 (ppg2 2_1) 89 b6 104 67 rto 2 4_0 (ppg2 4_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg24 when it is used in ppg2 output modes. - - 109 - rto 2 4_1 (ppg2 4_1) 90 c6 105 68 rto 2 5_0 (ppg2 4_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg24 when it is used in ppg2 output mo des. - - 108 - rto 2 5_1 (ppg2 4_1) 91 a5 106 69 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 43 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 9 e1 14 87 ain0_1 40 j6 45 18 ain0_2 2 c1 2 80 bin0_0 qprc ch.0 bin input pin 10 e2 15 88 bin0_1 41 l7 46 19 bin0_2 3 c2 3 81 zin0_0 qprc ch.0 zin input pin 11 e3 16 89 zin0_1 42 k7 47 20 zin0_2 4 b3 4 82 quadrature position/ revolution counter 1 ain1_1 qprc ch.1 ain input pin 74 c10 89 52 ain1_2 43 h6 48 21 bin1_1 qprc ch.1 bin input pin 73 c11 88 51 bin1_2 44 j7 49 22 zin1_1 qprc ch.1 zin input pin 72 e8 87 50 zin1_2 45 k8 50 23 quadrature position/ revolution counter 2 ain2_0 qprc ch.2 ain input pin - - 10 - ain2_1 83 d9 98 61 bin2_0 qprc ch.2 bin input pin - - 11 - bin2_1 84 a7 99 62 zin2_0 qprc ch.2 zin input pin - - 12 - zin2_1 85 b7 100 63 real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 92 b5 107 70 rtcco_1 55 h10 65 33 rt cco_2 19 g3 24 97 subout_0 sub clock output pin 92 b5 107 70 subout_1 55 h10 65 33 subout_2 19 g3 24 97 d a t a s h e e t 44 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 201 5 confidential module pin name function pin no lqfp - 100 bga - 1 12 lqfp - 120 qfp - 1 00 reset initx external reset input pin . a reset is valid when in itx="l". 38 k4 43 16 mode md0 mode 0 pin. during normal operation, md0="l" must be input. during serial programming to f lash memory, md0="h" must be input. 47 l8 57 25 md1 mode 1 pin. during serial programming to f lash memory, md1="l" must be input. 46 k9 56 24 power vcc power supply pin 1 b1 1 79 vcc power supply p in 26 j1 31 4 vcc power supply pin 35 k1 40 13 vcc power supply pin 51 k11 61 29 vcc power supply pin 76 a10 91 54 vcc power supply pin 97 a4 117 75 gnd vss gnd pin - b2 - vss g nd pin 25 l1 30 3 vss gnd pin - k2 - vss gnd pin - j3 - vss gnd pin - h4 - vss gnd pin 34 l4 39 12 vss gnd pin 50 l11 60 28 vss gnd pin - k10 - vss gnd pin - j9 - vss gnd pin - h8 - vss gnd pin - b10 - vss gnd pin - c9 - vss g nd pin 75 a11 90 53 vss gnd pin - d8 - vss gnd pin - d4 - vss gnd pin - c3 - vss gnd pin 100 a1 120 78 clock x0 main clock (oscillation) input pin 48 l9 58 26 x0a sub clock (oscillation) input pin 36 l3 41 14 x1 main clock (oscillation) i/o pin 49 l10 59 27 x1a sub clock (oscillation) i/o pin 37 k3 42 15 crout _0 built - in high - speed cr - osc clock output port 74 c10 89 52 crout _1 92 b5 107 70 analog power avcc a/d converter analog power pin 60 h11 70 38 avrh a/d converter analog refer ence voltage input pin 61 f11 71 39 analog gnd avss a/d converter gnd pin 62 g11 72 40 c pin c power stabilization capacity pin 33 l2 38 11 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 45 confidential ? i/o c ircuit t ype type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma b ? cmos level hysteresis input ? pull - up resistor : approximately 50 k p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor d igital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control pull - up resistor digital in put d a t a s h e e t 46 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential type circuit remarks c ? open drain output ? cmos level hysteresis input d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resis tor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resist or digital input digital out put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control n-ch d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 47 confidential type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with sta ndby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off ? +b input is available digital output digital output pull - up resistor control digital input standby mode control digital output digital output pull - up resistor control digital input standby mode control analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r d a t a s h e e t 48 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 20.5 ma, i ol = 18.5 ma digital output digital output pull - up resistor control digital input standby mode contr ol digital output digital output digital input standby mode control p-ch p-ch n-ch r p-ch n-ch r d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 49 confidential type circuit remarks i ? cmos level output ? cmos level hysteresis input ? with pull - up resistor c ontrol ? 5 v tolerant ? with standby mode control ? i oh = - 4 ma, i ol = 4 ma ? available to control of pzr registers. ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off j cmos level hysteresis input digital output digital output pull - up resistor control digital input standby mode control mode input p-ch p-ch n-ch r d a t a s h e e t 50 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? h andling p recations any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes preca utions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 1. precautions for product design this section describes precautions when designing electronic equipment using semiconduc tor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? rec ommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within th e recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power su pply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to perman ent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of ope ration. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltag es, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latc h - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute max imum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. code: ds00 - 00004 - 3 e d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 51 confidential ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor devi ces have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current l evels and other abnormal operating conditions. ? precautions related to usage of devices spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and me asurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or wh ere extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before su ch use. the company will not be responsible for damages arising from such use without prior approval. 2. precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during sol dering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liqui d solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditions. if socket mountin g is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mo unting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susc eptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. us ers are advised to mount packages in accordance with spansion ranking of recommended conditions. d a t a s h e e t 52 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduc ed under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a pa ckage that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. sto re products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% t o 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing p ackages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125 c /24 h ? static electri city because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other hi ghly static - prone materials for storage of completed board assemblies. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 53 confidential 3. precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to ch emical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments invol ving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives. please check the latest handling precautions at the following url. http :// www.spansion .com/ fjdocuments/ fj/ datasheet/e - ds/ds00 - 00004 .pdf d a t a s h e e t 54 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? h andling d evices ? power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions suc h as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power pins and gnd pins of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capaci tor between each power supply pin and gnd pin , between avcc pin and avss pin near this device. ? stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended o perating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. ? crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the p rinted circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. ? using an external clock when using an external clock, the clock signal sh ould be input to the x0 , x0a pin only and the x1 , x1a pin should be kept open. ? handling when using multi - function serial pin as i 2 c pin if it is using multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disable. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to external i 2 c bus system with power off. ? example of using an external clock device x0(x0a) x1(x1a) open d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 55 confidential ? c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the reg ulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to t hermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. ? mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between th e mode pins and v cc pins or v ss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously s witching to test mode due to noise. ? notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter, connect avcc = vcc and avss = vss. turning on : vcc vcc ? serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider th e case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected , retransmit the data. ? differences in features among the products with different memory sizes and between flash p roducts and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash products and mask products are differ ent because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. ? pull - up function of 5 v tolerant i / o please do not input the signal more than vcc voltage at the time of pull - up function use of 5 v tolerant i / o. device c vss c s gnd d a t a s h e e t 56 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? b lock d iagram ? m emory s ize see " ? p roduct l ineup " of " ? memory size " to confirm the memory size. m a i n f l a s h i / f c o r t e x - m 3 c o r e 1 4 4 m h z ( m a x ) c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . m u l t i - f u n c t i o n t i m e r x 3 m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 4 - c h . 7 ) h w f l o w c o n t r o l ( c h . 4 ) 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 3 c h . 1 6 - b i t p p g 3 c h . w a t c h c o u n t e r g p i o c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 - p i n + n m i t p i u r o m t a b l e e t m s r a m 0 8 / 1 6 / 2 4 / 3 2 k b y t e s w j - d p s r a m 1 8 / 1 6 / 2 4 / 3 2 k b y t e i d s y s m b 9 b f 4 1 2 n / r , m b 9 b f 4 1 4 n / r , m b 9 b f 4 1 5 n / r , m b 9 b f 4 1 6 n / r b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y t r s t x , t c k , t d i , t m s t r a c e d [ 3 : 0 ] , t r a c e c l k t i o a [ 7 : 0 ] t i o b [ 7 : 0 ] i c 0 [ 3 : 0 ] d t t i [ 2 : 0 ] x r t o 0 [ 5 : 0 ] f r c k [ 2 : 0 ] t d o s c k [ 7 : 0 ] s i n [ 7 : 0 ] s o t [ 7 : 0 ] i n t [ 1 5 : 0 0 ] n m i x p 0 [ f : 0 ] , p 1 [ f : 0 ] , . . . p x [ x : 0 ] i n i t x m o d e - c t r l i r q - m o n i t o r p i n - f u n c t i o n - c t r l m d [ 1 : 0 ] q p r c 3 c h . a i n [ 2 : 0 ] b i n [ 2 : 0 ] z i n [ 2 : 0 ] l v d c t r l c r c a c c e l e r a t o r i c 1 [ 3 : 0 ] r t s 4 c t s 4 e x t e r n a l b u s i / f m a d [ 2 4 : 0 0 ] m a d a t a [ 1 5 : 0 0 ] m c s x [ 7 : 0 ] , m a l e , m o e x , m w e x , m n a l e , m n c l e , m n w e x , m n r e x , m d q m [ 1 : 0 ] r t o 1 [ 5 : 0 ] m p u t r a c e b u f f e r ( 1 6 k b y t e ) i c 2 [ 3 : 0 ] r t o 2 [ 5 : 0 ] t x 1 , r x 1 c a n t x 0 , r x 0 c a n m a i n f l a s h 1 2 8 k b y t e / 2 5 6 k b y t e / 3 8 4 k b y t e / 5 1 2 k b y t e l v d p o w e r o n r e s e t r e g u l a t o r c w o r k f l a s h 3 2 k b y t e w o r k f l a s h i / f a h b - a h b b r i d g e c a n p r e s c a l e r r e a l - t i m e c l o c k r t c c o s u b o u t m r d y u n i t 0 1 2 - b i t a / d c o n v e r t e r 3 u n i t 1 u n i t 2 a v c c , a v s s , a v r h a n [ 1 5 : 0 0 ] a d t g [ 8 : 0 ] x 0 x 1 x 0 a p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z a h b - a p b b r i d g e : a p b 0 ( m a x 7 2 m h z ) m u l t i - l a y e r a h b ( m a x 1 4 4 m h z ) a h b - a p b b r i d g e : a p b 1 ( m a x 7 2 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 7 2 m h z ) d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 57 confidential ? m emory m ap ? memory map (1) peripherals area 0x41ff_ffff reserved 0x4006_4000 0x4006_3000 can ch.1 0x4006_2000 can ch.0 0x4006_1000 reserved 0x4006_0000 dmac reserved 0x4004_0000 0x4003_f000 ext - bus i/f 0x4003_c000 reserved 0x4003_b000 rtc 0x4003_a000 watch counter 0x4003_9000 crc 0x4003_8000 mfs 0x4003_7000 can prescaler 0x4003_ 6 000 reserved 0x4003_5000 lvd ctrl 0x4003_4000 reserved 0x4003_ 3 000 gpio 0x4003_2000 reserved 0x4003_1000 int - req. read 0x4003_0000 exti 0x4002_f000 reserved 0x4002_e000 cr trim 0x4002_8000 reserved 0x4002_7000 a/dc 0x4002_6000 qprc 0x4002_5000 base timer 0x4002_4000 ppg 0x4002_3000 reserved 0x4002_2000 mft unit2 0x4002_1000 mft unit1 0x4002_0000 mft unit0 0x4001_6000 reserved 0x4001_5000 dual timer 0x4001_3000 reserved 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 reserved 0x4000_0000 mainflash i/f 0xffff_ffff reserved 0xe010_0000 0xe000_0000 cortex - m3 private peripherals 0x 7 000_0000 reserved 0x6000_0000 external device area 0x4400_0000 reserved 0x4200_0000 32mbyte bit band alias 0x4000_0000 peripherals 0x2400_0000 reserved 0x2200_0000 32mbyte bit band alias 0x200e_1000 reserved see the next page " ? memory map (2), (3)" for the memory size deta i ls . 0x200e_0000 workflash i / f 0x200c_0000 workflash 0x2008_0000 reserved 0x2000_0000 sram1 0x1fff_0000 sram0 0x0010_2000 reserved 0x0010_0000 security/cr trim 0x00 0 0_0000 mainflash d a t a s h e e t 58 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? memory map (2) *: see " mb9 b510r/4 10r/310r/110r series flash programming m anual " for sector s tructure of flash. mb9bf 4 1 6 n/r 0x200e_0000 reserved workflash 32kbyte 0x200 c _ 8 000 0x200 c _ 0 000 sa0 - 3 (8kbx4) 0x2000_8000 reserved 0x2000_00 00 sram1 32kbyte 0x1fff_8000 sram0 32kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 security 0x0008_0000 reserved 0x0000_0000 sa10 - 15 (64kbx6) mainflash 512kbyte sa8 - 9 (48kbx2) sa4 - 7 (8kbx4) mb 9bf 4 15n/r 0x200e_0000 reserved workflash 32kbyte 0x200c_ 8 000 0x200c_0000 sa0 - 3 (8kbx4) 0x2000_6000 reserved 0x200 0 _0000 sram1 24kbyte 0x 1fff _ a 000 sram0 24kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 securit y 0x0006_0000 reserved 0x0000_0000 sa10 - 13 (64kbx4) mainflash 384 kbyte sa8 - 9 (48kbx2) sa4 - 7 (8kbx4) d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 59 confidential ? memory map (3) *: see " mb9 b510r/410r/310r/110r series flash programming m anual " for sector s tructure of flash. mb9bf 4 14n/r 0x200e_0000 reserved workflash 32kbyte 0x200c_ 8 000 0x200c_0000 sa0 - 3 (8kbx4) 0x2000_4000 reserved 0x2000_0000 sram1 16kbyte 0x1fff_c000 sram0 16 kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 security 0x0004_0000 reserved 0x0000_0000 sa10 - 11 (64kbx2) mainflash 256 kbyte sa8 - 9 (48kbx2) sa4 - 7 (8kbx4) mb9bf 4 12n/r 0x 200e_0000 reserved workflash 32kbyte 0x200c_ 8 000 0x200c_0000 sa0 - 3 (8kbx4) 0x2000_2000 reserved 0x2000_0000 sram1 8kbyte 0x1fff_e000 sram0 8kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 security 0x0002_0000 reserved 0x0000_0000 sa8 - 9 (48kbx2) mainflash 128 kbyte sa4 - 7 (8kbx4) d a t a s h e e t 60 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? perip heral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb main flash i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2 000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit 0 0x4002_1000 0x4002_1fff multi - function timer unit 1 0x4002_2000 0x4002_3fff multi - function timer unit2 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff res erved 0x4002_e000 0x4002_efff internal cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt controller 0x4003_1000 0x4003_1fff interrupt request batch - read function 0x4003_2000 0x4003_2fff reserved 0x4003_3 000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_5fff low - voltage detector 0x4003_6000 0x4003_6fff reserved 0x4003_7000 0x4003_7fff can prescaler 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003 _9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_ b fff real - time clock 0x4003_ c 000 0x4003_efff reserved 0x4003_f000 0x4003_ffff external memory interface 0x4004_0000 0x400 5 _ffff ahb reserved 0x4006_0000 0x4006_0fff dmac registe r 0x4006_ 1 000 0x4006_ 1 fff reserved 0x4006_ 2 000 0x4006_ 2 fff can ch.0 0x4006_ 3 000 0x4006_ 3 fff can ch. 1 0x4006_ 4 000 0x41ff_ffff reserved 0x 2 00 e _0000 0x 2 00 e _ f fff work f lash i / f register d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 61 confidential ? p in s tatus in e ach cpu s tate the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the " l " level. ? initx=1 this is the period when the initx pin is the " h " level. ? spl=0 this is the status that standby pi n level setting bit (spl) in standby mode control register (stb_ctl) is set to " 0 " . ? spl=1 this is the status that standby pin level setting bit (spl) in standby mode control register (stb_ctl) is set to " 1 " . ? input enabled indicates that the input function can be used. ? internal input fixed at " 0 " this is the status that the input function cannot be used. internal input is fixed at " l " . ? hi - z indicates that the output drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a po rt, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. d a t a s h e e t 62 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? l ist of p in s tatus pin status type function group power - on reset or low - voltage detection sta te initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled in put enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator output pin hi - z/ internal input fixed at " 0 " / or input enable hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop * 1 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop * 1 / internal input fixed at " 0 " c init x input pin pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled e jtag selected hi - z pull - up/ input enabled pull - up/ input enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z/ internal input fixed at " 0 " f trace selecte d setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output external interrupt enabled selected maintain previous state gpio selected, or other than above resource selected hi - z hi - z/ input ena bled hi - z/ input enabled hi - z/ internal input fixed at " 0 " d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 63 confidential pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 g trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state tr ace output gpio selected, or other than above resource selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " h external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous s tate maintain previous state maintain previous state gpio selected, or other than above resource selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " i gpio selected, resource selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " j nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or other than above resource selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " d a t a s h e e t 64 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential pin s tatus type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or s leep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 k analog input selected hi - z hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled gpio sel ected, or other than above resource selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " l external interrupt enabled selected setting disabled setting disabled setti ng disabled maintain previous state maintain previous state maintain previous state analog input selected hi - z hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled gpio selected, or other than above resource selected setting disabled setting disabled setting disabled maintain prev ious state maintain previous state hi - z/ internal input fixed at " 0 " m gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator input pin in put enabled input enabled input enabled input enabled input enabled input enabled d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 65 confidential pin s tatus type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or s leep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 n gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator output pin hi - z/ internal input fixed at " 0 " / or input enable hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop * 2 / internal input fixed a t " 0 " maintain previous state/ hi - z at oscillation stop * 2 / internal input fixed at " 0 " o gpio selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " p mode input pin input e nabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ input enabled *1: oscillation is stopped at s ub t imer mod e , low - speed cr t imer mode, and s top mode. *2: oscillation is stopped at s top mode. d a t a s h e e t 66 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? e lectrical c haracteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1 , * 2 v cc v ss - 0.5 v ss + 6.5 v analog power supply voltage * 1 , * 3 a v cc v ss - 0.5 v ss + 6.5 v analog reference voltage * 1 , * 3 av rh v ss - 0.5 v ss + 6.5 v input voltage* 1 v i v ss - 0.5 v cc + 0.5 ( ss - 0.5 v ss + 6.5 v 5 v tolerant analog pin input voltage* 1 v ia v ss - 0.5 a v cc + 0.5 ( 1 v o v ss - 0.5 v cc + 0.5 ( clamp - 2 +2 ma * 7 clamp total maximum curre nt clamp ] +20 ma * 7 l level maximum output current* 4 i ol - 10 ma 4 ma type 20 ma 12 ma type 39 ma p80, p81 l level average output current* 6 i olav - 4 ma 4 ma type 12 ma 12 ma type 18.5 ma p80, p81 l level total maximum output current ol - 100 ma l level total average output current* 6 olav - 50 ma h level maximum output current* 4 i oh - - 10 ma 4 ma type - 20 ma 12 ma type - 39 ma p80, p81 h level average output current* 5 i ohav - - 4 ma 4 ma type - 12 ma 12 ma type - 20.5 ma p80, p81 h level total maximum output current oh - - 100 ma h level total average output current* 6 ohav - - 50 ma power consumption p d - 1000 mw storage temperature t stg - 55 + 150 c * 1 : the se parameters are based on the conditi on that v ss = a v ss = 0.0 v. * 2 : v cc must not drop below v ss - 0.5 v. * 3 : ensure that the voltage does not to exceed v cc + 0. 5 v , for example , when the power is turned on. * 4 : the maximum output current is the peak value for a single pin. * 5 : the average ou tput is the average current for a single pin over a period of 100 ms. * 6 : the total average output current is the average current for all pins over a period of 100 ms. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 67 confidential * 7 : ? see " l ist of p in f unctions " and " i/o c ircuit t ype " about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input. ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive cur rent is low, such as in the low - power consumpsion modes, the +b input potential may pass through the protective diode and increase the potential at the vcc and avcc pin, and this may affect other devices. ? note that if a +b signal is input when the device power supply is off (not fixed at 0v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a recommended circuit example (i/o equivalent circuit) . < warning > semiconductor devices can be permanently damaged by application of stress (voltage , current , temperature , etc.) in excess of absolute maximum ratings. do not exceed these ratings. r +b input (0v to 16v) protection diode p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output d a t a s h e e t 68 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential 2. recommended operating conditions ( v ss = a v ss = 0.0v) paramete r symbol conditions value unit remarks min max power supply voltage v cc - 2.7 * 2 5.5 v analog power supply voltage a v cc - 2.7 5.5 v a v cc = v cc analog reference voltage avrh - 2.7 a v cc v smoothing capacitor c s - 1 10 f 1 operating t emperature fpt - 1 00 p - m 20/m23 fpt - 1 20 p - m 21/m37 t a when mounted on four - layer pcb - 40 + 85 c fpt - 100p - m 36 bga - 112p - m04 t a - - 40 + 85 c * 1 : see " c pin " in " h andling d evices " for the connection of the smoothing capacitor. * 2 : in betwe en less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is used) or built - in low - speed cr is possible to operate only. < warning > the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. al ways use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses , operating conditions , or combi nations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 69 confidential 3. dc characteristics ( 1 ) current r ating ( v cc = a v cc = 2.7v to 5.5v , v ss = a v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks typ * 3 max * 4 r un mode current i cc v cc pll r un mode cpu : 144 mhz , peripheral : 72 mhz , main flash 2 wait tracebuffer : on frwtr.rwt = 10 fsyndn.sd = 000 fbfcr.be = 1 85 117 ma *1 , *5 cpu : 72 mhz , peripheral : 72 mhz , main flash 0 wait tracebuffer : off frwtr.rwt = 00 fsyndn.sd = 000 fbfcr.be = 0 52 70 ma *1 , *5 high - speed cr r un mode cpu/ peripheral : 4 mhz* 2 main flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 5 17 ma *1 sub r un mode cpu/ peripheral : 32 khz main flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 1.3 14 ma *1 , *6 low - speed cr r un mode cpu/ peripheral : 100 khz main flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 1.3 14 ma *1 s leep mode current i ccs pll s l eep mode peripheral : 72 mhz 28 43 ma *1 , *5 high - speed cr s leep mode peripheral : 4 mhz* 2 3 16 ma *1 sub s leep mode peripheral : 32 khz 1 14 ma *1 , *6 low - speed cr s leep mode peripheral : 100 khz 1 14 ma *1 *1: when a l l ports are fixed. *2: w hen setting it to 4 mhz by trimming. * 3 : t a =+25c, v cc = 5.5 v * 4 : t a =+ 8 5 c, v cc =5.5 v *5: when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) d a t a s h e e t 70 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential parameter symbol pin name conditions value unit remarks typ * 2 max * 2 t imer mode current i cct v cc main t imer mode t a = + 25 c , when lvd is off 3.2 6 ma *1 , *3 t a = + 85 c , when lvd is off - 1 5 ma *1 , *3 sub t imer mode t a = + 25 c , when lvd is off 0.9 3 ma *1 , *4 t a = + 85 c , when lvd is off - 12 ma *1 , *4 s top mode current i cch s top mode t a = + 25 c , when lvd is off 0.8 3 ma *1 t a = + 85 c , when lvd is off - 12 ma *1 *1: w hen a l l ports are fixed. * 2 : v cc =5.5 v * 3 : when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 4 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) low - v oltage d etection current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85 c) parameter symbol pin name conditions value unit remarks typ max low voltage detection circuit (lvd) power supply current i cclvd vcc at operation for interrupt v cc = 5.5 v 4 7 flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc mainflash at write/erase 11.4 13.1 ma * workflash at write/erase 11.4 13.1 ma *: the current at which to write or erase flash memory, i ccflash is added to i cc. a/d converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 85 c) parameter symbol pin name cond itions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.47 0.62 ma at stop 0.06 25 ccavrh avrh at 1unit operation avrh=5.5 v 1.1 1.96 ma at stop 0.06 4 d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 71 confidential ( 2 ) pin characteristics ( v cc = a v cc = 2.7v to 5.5v , v ss = a v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value u nit remarks min typ max h level input voltage (hysteresis input) v ihs cmos hysteresis input pin , md0 , md1 - v cc 0.8 - v cc + 0.3 v 5 v tolerant input pin - v cc 0.8 - v ss + 5.5 v l level input voltage (hysteresis input) v ils cmos hysteresis input pin , md0 , md1 - v ss - 0.3 - v cc 0.2 v 5 v tolerant input pin - v ss - 0.3 - v cc 0.2 v h level output voltage v oh 4 ma type v cc oh = - 4 ma v cc - 0.5 - v cc v v cc < 4.5 v i oh = - 2 ma 12 ma type v cc oh = - 12 ma v cc - 0.5 - v cc v v cc < 4.5 v i oh = - 8 ma p80, p81 v cc oh = - 20.5 ma v cc - 0.4 - v cc v v cc < 4.5 v i oh = - 13.0 m a d a t a s h e e t 72 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential parameter symbol pin name conditions value unit remarks min typ max l level output voltage v ol 4 ma type v cc ol = 4 ma v ss - 0.4 v v cc < 4.5 v i ol = 2 ma 12 ma type v cc ol = 12 ma v ss - 0.4 v v cc < 4.5 v i ol = 8 ma p80, p81 v cc o l = 18.5 ma v ss - 0.4 v v cc < 4.5 v i ol = 10.5 ma input leak current i il - - - 5 - + 5 pu pull - up pin v cc cc < 4.5 v 30 80 200 input capacita nce c in other than v cc, v ss, av cc, av ss, avrh - - 5 15 pf d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 73 confidential 4. ac characteristics (1) main clock input characteristics ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max input fre quency f ch x0 x1 v cc cc < 4.5 v 4 20 v cc cc < 4.5 v 4 20 input clock cycle t cylh v cc cc < 4.5 v 50 250 in put clock pulse width - p wh /t cylh p wl /t cylh 45 55 % when using external clock input clock rise time and fall time t cf , t cr - - 5 ns when using external clock internal operating c lock * 1 frequency f cm - - - 144 mhz master clock f cc - - - 144 mhz base clock (hclk/fclk) f cp0 - - - 72 mhz apb0 bus clock * 2 f cp1 - - - 72 mhz apb1 bus clock * 2 f cp 2 - - - 72 mhz apb2 bus clock * 2 internal operating clock * 1 cycle time t cycc - - 6.94 - ns base clock (hclk/fclk) t cycp0 - - 13.8 - ns apb0 bus clock * 2 t cy cp1 - - 13.8 - ns apb1 bus clock * 2 t cycp2 - - 13.8 - ns apb2 bus clock * 2 * 1 : for more information about each internal operating clock , see " c hapter 2 - 1 : clock " in " fm3 family peripheral manual " . * 2 : for about each apb bus which each peripheral is connec ted to , see " b lock d iagram " in this data sheet. x0 d a t a s h e e t 74 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential (2) sub clock input characteristics ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit r emarks min typ max input frequency 1/ t cyll x0a x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 wh /t cyll p wl /t cyll 45 - 55 % when using external clock (3) internal cr oscillation characteristics ? high - speed internal cr ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c 3.9 6 4 4.0 4 mhz when trimming * 1 t a = 0 c to + 70 c 3.84 4 4.16 t a = - 40 c to + 85 c 3.8 4 4.2 t a = - 40 c to + 85 c 3 4 5 w hen not trimming f requency stability time t crwt - - - 90 2 *1: in the case of using the values in cr trimming area of flash memory at shipment for frequency trimming. *2: f requency stable time is time to stable of the frequency of the high - speed cr . clock after the trim value is set. after setting the trim value, the period when the frequency stability time passes can use the high - speed cr clock as a source clock. ? low - speed internal cr ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz x0 a d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 75 confidential (4 - 1 ) operating conditions of main pll (in the case of using main clock for input of pll) ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symb ol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 4 - 16 mh z pll multiple rate - 13 - 75 multiple pll macro oscillation clock frequency f pllo 200 - 300 mh z main pll clock frequency* 2 f clkpll - - 40 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see " c hapter 2 - 1 : clock " in " fm3 family peripheral manual " . (4 - 2) ope rating conditions of main pll (in the case of using high - speed internal cr) ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 3.8 4 4.2 mh z pll multiple rate - 50 - 71 multiple pll macro oscillation clock frequency f pllo 190 - 300 mh z main pll clock frequency* 2 f clkpll - - 40 mh z * 1 : time from when the pll starts operating until the os cillation stabilizes. *2: for more information about main pll clock (clkpll), see " c hapter 2 - 1 : clock " in " fm3 family peripheral manual " . when setting pll multiple rate, please take the accuracy of the built - in high - speed cr clock into account and prevent the master clock from exceeding the maximum frequency. k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider ma in pll connection high - speed cr clock (clkhc) main clock (clkmo) d a t a s h e e t 76 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential (5) reset input characteristics ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max reset i nput time t initx initx - 500 - ns (6) power - on reset timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name value unit remarks min max power supply rising time t vcc r v cc 0 - ms power supply shut down time t off 1 - ms time until releasing power - on reset t prt 0.57 0.76 ms glossary ? vcc_minimum : minimum v cc of recommended operating conditions ? vdh_minimum : minimum release voltage of low - voltage detection reset. see " 6 . low - voltage detection characteristics " 0 . 2 v v d h _ m i n i m u m v c c _ m i n i m u m t p r t i n t e r n a l r e s e t v c c c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e t v c c r 0 . 2 v 0 . 2 v t o f f d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 77 confidential (7) external bus timing ? external bus clock output c haracteristics ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max out put freque ncy t cycle mclkout * 1 v cc 2 mhz v cc < 4.5 v - 32 * 3 mhz *1: external bus clock (mclkout) is divided clock of hclk. for more information about setting of clock divider , see " c hpater 12 : external bus interface " in " fm3 family peripheral manual " . when external bus cl ock is not output, this characteristic does not give any effect on external bus operation. *2 : when ahb bus clock frequency is more than 100mhz , the divider setting for mclkout must be more than 4. *3 : when ahb bus clock frequency is more than 64 mhz , the d ivider setting for mclkout must be more than 4. ? external bus signal input/output characteristics ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks signal input c haracteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output c haracteristics v oh 0.8 v cc v v ol 0.2 v cc v input signal output signal mclkout v ih v il v il v ih v oh v ol v ol v oh d a t a s h e e t 78 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? separate bus access asynchronous sram mode ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max moex min pulse width t oew moex v cc mclk n - 3 - ns v cc < 4.5 v mcsx csl C av mcsx[7:0] mad[24:0] v cc - 9 + 9 ns v cc < 4.5 v - 12 + 12 moex oeh - ax moex mad[24:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m +12 mcsx cs l - oe l moex mcsx[7:0] v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 moex oeh - c sh v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx cs l - r dqm l mcsx mdqm[1:0] v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 data set up ds - oe moex madata[15:0] v cc 20 - ns v cc < 4.5 v 38 - moex dh - oe moex madata[15:0] v cc 0 - ns v cc < 4.5 v m wex min pulse width t wew mwex v cc mclk n - 3 - ns v cc < 4.5 v mwex weh - ax mwex mad[24:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx csl - wel mwex m csx[7:0] v cc mclk n - 9 mclk n+9 ns v cc < 4.5 v mclk n - 12 mclk n+12 mwex weh - csh v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx cs l - w dqml mcsx mdqm[1:0] v cc mclk n - 9 mclk n+ 9 ns v cc < 4.5 v mclk n - 12 mclk n+12 mcsx cs l - dv mcsx madata[15:0] v cc - 9 mclk + 9 ns v cc < 4.5 v mclk - 12 mclk + 12 mwex weh - dx mwex madata[15:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 note: w hen the external load capacitance = 30 pf. (m = 0 to 15 , n = 1 to 16) d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 79 confidential mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d a d d r e s s t c s l - o e l t c s l - a v r d a d d r e s s w d t d h - o e t d s - o e t w e h - d x t o e w t o e h - a x t o e h - c s h t w e w t c y c l e t c s l - w e l t c s l - a v t w e h - c s h t w e h - a x t c s l - w d q m l t c s l - r d q m l t c s l - d v d a t a s h e e t 80 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? separate bus access synchronous sram mode ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max address delay time t av mclk mad[24:0] v cc cc < 4.5 v 12 mcsx delay time t csl mclk mcsx[7:0] v cc cc < 4.5 v 12 t cs h v cc cc < 4.5 v 12 moex delay time t rel mclk moex v cc cc < 4.5 v 12 t reh v cc cc < 4.5 v 12 data set up ds mclk madata[15:0] v cc - ns v cc < 4.5 v 37 mclk dh mclk madata[15:0] v cc - ns v cc < 4.5 v mwex delay time t wel mclk mwex v cc cc < 4.5 v 12 t we h v cc cc < 4.5 v 12 mdqm[1:0] delay time t dqml mclk mdqm[1:0] v cc cc < 4.5 v 12 t dqmh v cc cc < 4.5 v 12 mclk ods mclk, madata[15:0] v cc cc < 4.5 v mclk+24 mclk od mclk madata[15:0] v cc cc < 4.5 v 24 note: w hen the external load capacitance = 30 pf. mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 81 confidential ? multiplexed bus access asynchronous sram mode ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max multiplexed a ddress delay time t a le - chmadv male madata[15:0] v cc cc < 4.5 v 20 multiplexed a ddress hold time t c hmadh v cc cc < 4.5 v mclk n+0 mclk n+20 note: w hen the external load capacitance = 30 pf. (m = 0 to 15 , n = 1 to 16) mc lk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0] d a t a s h e e t 82 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? multiplexed bus access synchronous sram mode ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk ale v cc cc < 4.5 v 1 2 ns t chah v cc cc < 4.5 v 12 ns mclk chmadv m clk madata[15:0] v cc od ns v cc < 4.5 v mclk chmad x v cc od ns v cc < 4.5 v note: w hen the external load capacitance = 30 pf. mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0] d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 83 confidential ? nand flash mode ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to +85 c ) parameter symbol pin name conditions value unit min max m nrex min pulse width t nrew mnrex v cc mclk n - 3 - ns v cc < 4.5 v data setup ds C nre mnrex madata[15:0] v cc 20 - ns v cc < 4.5 v 38 - mnrex dh C nre mnrex madata[15:0] v cc 0 - ns v cc < 4.5 v mnale aleh - nwel mnale mnwex v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 mnale ale l - nwel mnale mnwex v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 mncle cleh - nwel mncle mnwex v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 mnwex nweh - clel mncle mnwex v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mnwex min pulse width t nwew mnwex v cc mclk n - 3 - n s v cc < 4.5 v mnwex nwel C dv mnwex madata[15:0] v cc - 9 + 9 ns v cc < 4.5 v - 12 +12 mnwex nweh C dx mnwex madata[15:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 note: w hen the exte rnal load capacitance = 30 pf. (m=0 to 15 , n=1 to 16) d a t a s h e e t 84 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential nand f lash read mclk mnrex madata [ 15 : 0 ] read d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 85 confidential nand flash a ddress w rite nand flash command write mclk mnale mncle madata [ 15 : 0 ] mnwex write mclk mnale mncle madata [ 15 : 0 ] mnwex write d a t a s h e e t 86 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? external ready input timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max mclk rdyi mclk mrdy v cc cc < 4.5 v 37 ? when rdy is input ? when rdy is release d mclk original moex mwex mrdy mclk extended moe x mwex mrdy over 2cycle t rdyi 2 cycle t rdyi 0.5vcc d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 87 confidential (8) base timer input timing ? timer input timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks m in max input pulse width t tiwh t tiwl tioan/tiobn (when using as eck , t in) - 2 t cycp - ns ? trigger input timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter sy mbol pin name conditions value unit remarks min max input pulse width t trgh t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note: t cycp indicates the apb bus clock c ycle time. about the apb bus number which base timer is connected to , see " b lock d iagram " in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l d a t a s h e e t 88 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential (9) csio/ uart timing ? csio (spi = 0 , scinv = 0) ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t sc yc sck x master mode 4 t cycp - 4 t cycp - ns sck slovi sckx sotx - 30 +30 - 20 + 20 ns sin ivshi sckx sinx 50 - 30 - ns sck shixi sckx sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck slove sckx sotx - 50 - 30 ns sin ivshe sckx sinx 10 - 10 - ns sck shixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is co nnected t o , see " b lock d iagram " in this data sheet. ? these characteristics only guarantee the same relocate port number. for example , the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 89 confidential m aster mode slave mode t slsh t shsl v ih t f t r v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi sck sot sin d a t a s h e e t 90 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? csio (spi = 0 , scinv = 1) ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t sc yc sckx master mode 4 t cycp - 4 t cycp - ns sck shovi sckx sotx - 30 +30 - 20 + 20 ns sin ivsli sckx sinx 50 - 30 - ns sck slixi sckx sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck shove sckx sotx - 50 - 30 ns sin ivsle sckx sinx 10 - 10 - ns sck slixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is co nnected to , see " ? these characteristics only guarantee the same relocate port number. for example , the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 91 confidential master mode slave mode t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove t scyc v oh v oh v o h v ol v ol v ih v il v ih v il t shovi t ivsli t slixi sck sot sin d a t a s h e e t 92 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? csio (spi = 1 , scinv = 0) ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max ser ial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck shovi sckx sotx - 30 +30 - 20 + 20 ns sin ivsli sckx sinx 50 - 30 - ns sck slixi sckx sinx 0 - 0 - ns sot sovli sckx sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck shove sckx s ot x - 50 - 30 ns sin ivsle sckx sinx 10 - 10 - ns sck slixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indi cates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " ? these characteristics only guarantee the same relocate port number. for example , the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 93 confidential master mode slave mode *: changes when writing to tdr register t f t r t slsh t shsl t shove v i l v i l v ih v ih v ih v oh * v o l v oh v o l v ih v i l v ih v i l t ivsle t slixe sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivsli t slixi sck sot sin d a t a s h e e t 94 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? csio (spi = 1 , scinv = 1) ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck slovi sckx sotx - 30 +30 - 20 + 20 ns sin ivshi sckx sinx 50 - 30 - ns sck shixi sckx sinx 0 - 0 - ns sot sovhi sckx sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck slove sckx s ot x - 50 - 30 ns sin ivshe sckx sinx 10 - 10 - ns sck shixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes: ? the above characteristics ap ply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " ? these characteristics only guarantee the same relocate port numbe r. for example , the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 95 confidential master mode slave mode ? uart e xte rnal clock input (ext = 1) ( v cc = 2. 7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol conditions min max unit remarks serial clock l pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock h pulse width t shsl t cycp + 10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns t shsl t r t slsh t f t slove v il v il v il v ih v ih v oh v o l v oh v o l v ih v il v ih v il t ivshe t shixe sck sot sin t scyc t slovi v ol v oh v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivshi t shixi t sovhi sck sot sin t shsl v i l v i l v i l v ih v ih t r t f t slsh s ck d a t a s h e e t 96 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential (10) external input timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t inh , t inl adtg - 2 t cycp * - ns a/d converte r trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * - ns wave form generator int xx, nmix except timer mode, stop mode 2 t cycp + 100 * - ns external interrupt nmi timer mode, stop mode 500 - ns *1: t cycp indicates the apb bus clock cycle time. about the apb bus number which a/d converter , multi - function timer , externa l interrupt is connected t o , see " b lock d iagram " in this data sheet. d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 97 confidential (11) quadrature position/revolution counter timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol conditions value unit min max ain pin h width t ahl - 2 t cycp * - ns ain pin l width t all - bin pin h width t bh l - bin pin l width t bll - bin rise time from ain pin h level t aubu pc_mode2 or pc_ m ode3 ain fall time from bin pin h level t buad pc_mode2 or pc_mode3 bin fall time from ain pin l level t adbd pc_mode2 or pc_mode3 ain rise time from bin pin l level t bdau pc_mode2 or pc_mode3 ain rise time from bin pin h level t buau pc_mode2 or pc_mode3 bin fall time from ain pin h level t aubd pc_mode2 or pc_mode3 ain fall time from bin pin l level t bdad pc_mode2 or pc_mode3 bin rise time from ain pin l level t adbu pc_mode2 or pc_mode3 zin pin h width t zhl qcr:cgsc=0 zin pin l width t zll qcr:cgsc=0 ain/bin rise and fall time from determined zin level t zabe qcr:cgsc=1 determined zin level from ain/bin rise and fall tim e t abez qcr:cgsc=1 *: t cycp indicates the apb bus clock cycle time. about the apb bus number which quadrature position/revolution counter is connected t o , see " b lock d iagram " in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll d a t a s h e e t 98 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 99 confidential (12) i 2 c timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol conditions standard - mode fast - mode un it remarks min max min max scl clock frequency f scl c l = 30 pf , r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda hdsta 4.0 - 0.6 - low 4.7 - 1.3 - high 4.0 - 0.6 - susta 4.7 - 0.6 - hddat 0 3.45* 2 0 0.9* 3 sudat 250 - 100 - ns stop condition setup time scl susto 4.0 - 0.6 - buf 4.7 - 1.3 - sp 8 mhz cycp cycp * 4 - 2 t cycp * 4 - ns *5 40 mhz < t cycp cycp * 4 - 3 t cycp * 4 - ns *5 60 mhz < t cycp cycp * 4 - 4 t cycp * 4 - ns *5 *1: r and c represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2: the maximum t hddat must satisfy that it doesn't extend at least l period (t low ) of device's scl signal. *3: fast - mode i 2 c bus device can be used on s tandard - mode i 2 c bus system as long as the device satisfies the requirement of t sudat 250 ns. *4: t cycp is the apb bus clock cycle time. about the apb bus number that i2c is connected to, see " b lock d iagram " in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more. to use fast - mode, set the apb bus clock at 8 mhz or more. *5: the number of the steps of the noise f ilter can be changed by register settings. change the number of the noise filter steps according to apb2 bus clock frequency. sda s cl d a t a s h e e t 100 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential (13) etm timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk traced [3:0] v cc 4.5 cc < 4.5 v 2 15 traceclk frequency 1/ t trace traceclk v cc 4.5 cc < 4.5 v - 32 mhz traceclk c ycle time t trace v cc 4.5 cc < 4.5 v 31.25 - ns note: when the external load capacitance = 30 pf . hcl k traceclk traced[3:0] d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 101 confidential (14) jtag timing ( v cc = 2.7v to 5.5v , v ss = 0v , t a = - 40 c to + 85 c ) parameter symbol pin name conditions valu e unit remarks min max tms , tdi setup time t jtags tck , tms , tdi v cc cc < 4.5 v tms , tdi hold time t jtagh tck , tms , tdi v cc cc < 4.5 v tdo delay time t jtagd tck , tdo v cc cc < 4.5 v - 45 note: when the external load capacitance = 30 pf . tck tms/ tdi tdo d a t a s h e e t 102 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential 5. 12 - bit a/d converter ? electrical c haracteristics for the a/d c onverter ( v cc = a v cc = 2.7v to 5.5v , v ss = a v ss = 0 v , t a = - 40 c to + 85 c ) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 4.0 4.5 lsb avrh = 2.7 v to 5.5 v differential nonlinearity - - - 2.3 2.5 lsb zero transition volt age v z t an xx - 10 15 mv full - scale transition voltage v fst an xx - avrh 10 avrh 15 mv conversion time - - 1.0* 1 - - cc 1 - - a v cc < 4.5 v sampling time t s - *2 - - ns av cc cc < 4.5 v compare clock cy cle* 3 t cck - 50 - 2000 ns av cc cc < 4.5 v state transition time to operation permission t stt - - - 1.0 ain - - - 12.9 pf analog input resistance r ain - - - 2 k cc cc < 4.5 v interch annel disparity - - - - 4 lsb analog port input current - an xx - - 5 ss - avrh v reference voltage - avrh 2.7 - a v cc v *1: conversion time is the value of sampling time ( t s ) + compare time ( t c ). the condition of the minimum conversion time is the following. a v cc 4.5 v, hclk= 120 hz sampling time: 3 00 n s , compare time: 700 n s a v cc < 4.5 v, hclk= 120 hz sampling time: 500 ns, compare time: 700 ns ensure that it satisfies the value of sampling time ( t s ) and comp are clock cycle ( t cck ). for setting * 4 of sampling time and compare clock cycle, see " c hapter 1 - 1 : 12 - bit a/d converter " in " fm3 family peripheral manual analog macro part " . a / d c onverter register is set at apb bus clock timing. sampling and compare clock i s set at base clock (hclk). about the apb bus number which the a/d converter is connected to, see " b lock d iagram " in this data sheet. *2: a necessary sampling time changes by external impedance. ensure that it set the sampling time to satisfy ( equation 1 ). *3: compare time ( t c ) is the value of ( equation 2). d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 103 confidential (equation 1) t s ( r ain + r ext ) c ain 9 t s : sampling time r ain : input resistance of a/d = 2 k at 4.5 v < av cc < 5.5 v input resistance of a/d = 3.8 k at 2.7 v < av cc < 4 .5 v c ain : input capacity of a/d = 12.9 pf at 2.7 v < av cc < 5.5 v r ext : output impedance of external circuit (equation 2 ) t c = t cck 14 t c : compare time t cck : compare clock cycle r ext r ain c ain analog signal source an xx analog input pin c omparator d a t a s h e e t 104 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? definition of 1 2 - bit a/d converter terms ? reso lution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) fro m the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v z t } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v z t 4094 n: a/d converter digital output value. v z t : voltage at which the digital output changes from 0x000 to 0x0 01. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh av ss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 105 confidential 6. low - v oltage d etection c haracteristics (1) low - v oltage d etection r eset ( t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl - 2.25 2.45 2.65 v when voltage drops released voltage vdh - 2.30 2.50 2.70 v when voltage rises ( 2 ) interrupt of l ow - v oltage d etection ( t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 0000 2.58 2.8 3.02 v when voltage drops released voltage vdh 2.67 2.9 3.13 v when voltage rises detected voltage vdl svhi = 0001 2.76 3.0 3.24 v when voltage drops released v oltage vdh 2.85 3.1 3.34 v when voltage rises detected voltage vdl svhi = 0010 2.94 3.2 3.45 v when voltage drops released voltage vdh 3.04 3.3 3.56 v when voltage rises detected voltage vdl svhi = 0011 3.31 3.6 3.88 v when voltage drops released vol tage vdh 3.40 3.7 3.99 v when voltage rises detected voltage vdl svhi = 0100 3.40 3.7 3.99 v when voltage drops released voltage vdh 3.50 3.8 4.10 v when voltage rises detected voltage vdl svhi = 0111 3.68 4.0 4.32 v when voltage drops released volta ge vdh 3.77 4.1 4.42 v when voltage rises detected voltage vdl svhi = 1000 3.77 4.1 4.42 v when voltage drops released voltage vdh 3.86 4.2 4.53 v when voltage rises detected voltage vdl svhi = 1001 3.86 4.2 4. 53 v when voltage drops released voltage vdh 3.96 4.3 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 4032 t cycp * cycp indicates the apb2 bus clock cycle time. d a t a s h e e t 106 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential 7. mainflash memory write/erase characteristics (1) write / erase time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 85 c ) parameter value unit remarks typ* max* sector erase time large sector 0. 7 3.7 s includ es write time prior to internal erase small sector 0.3 1.1 half word (16 - bit) write time 12 384 erase/write cycles (cycle) d ata hold time (year ) remarks 1 , 000 20* 10 , 000 10* 100 , 000 5* *: at average + 85 ? c 8. work flash memory write/erase characteristics (1) write / erase time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 85 c ) parameter value unit remarks typ* max* sector era se time 0.3 1.5 s includ es write time prior to internal erase half word (16 - bit) write time 20 384 erase/write cycles (cycle) data hold time (year ) remarks 1 , 000 20* 10 , 000 10* *: at average + 85 ? c d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 107 confidential 9. return time from low - powe r consumption mode (1 ) return f actor: interrupt the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. ? return count time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 8 5 c ) parameter symbol value unit remarks typ max* s leep mode t icnt t cycc ns high - speed cr t imer mode, main t imer mode, pll t imer mode 40 80 ? operation example of return from low - power consumption mode (by external interrupt*) *: external interrupt is set to detecting fall edge. e x t e r n a l i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t 108 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power co nsumption modes. see " chapter 6: low power consumption mode and operations of standby modes " in " fm3 family peripheral manual " about the return factor from low - power consumption mode. ? when interrupt recoveries, the operation mode that cpu recoveries dep ends on the state before the low - power consumption mode transition. see " chapter 6: low power consumption mode " in " fm3 family peripheral manual " . i n t e r n a l r e s o u r c e i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 109 confidential (2) return f actor: reset the return time from low - power consumption mode is indicated as follows. it is f rom releasing reset to starting the program operation. ? return count time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 8 5 c ) parameter symbol value unit remarks typ max* s leep mode t rcnt 321 461 ? operation example of return from low - power consumption mode (by initx) i n i t x t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e d a t a s h e e t 110 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see " c hapter 6 : low power consumption mode and operations of standby modes " in " fm3 family peripheral manual " . ? when interrupt recoveries, the operation mode that cpu recoveries depends on th e state before the low - power consumption mode transition. see " chapter 6: low power consumption mode " in " fm3 family peripheral manual " . ? the time during the power - on reset/low - voltage detection reset is excluded. see " (6) power - on reset timing " in " 4. ac characteristics " in " ? when in recovery from reset, cpu changes to the h igh - speed cr r un mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the m ain pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r e s e t t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 111 confidential ? o rdering i nformation part number on - chip flash memory on - chip sram package packing mb9bf 4 1 2np qc - jne2 main: 128 kbyte work: 32 kbyte 8 kbyte plastic ? qfp 1 00 - pin (0. 6 5 mm pitch) , (fpt - 1 00 p - m0 3 ) tray mb9bf 4 1 4np qc - jne2 main: 256 kbyte work: 32 kbyte 16 kby te mb9bf415np qc - jne2 main: 384 kbyte work: 32 kbyte 24 kbyte mb9bf 4 1 6np qc - jne2 main: 512 kbyte work: 32 kbyte 32 kbyte mb9bf 4 1 2npmc - jne2 main: 128 kbyte work: 32 kbyte 8 kbyte plastic ? lqfp 1 00 - pin (0.5 mm pitch) , (fpt - 1 00 p - m23 ) mb9bf 4 1 4npmc - jn e2 main: 256 kbyte work: 32 kbyte 16 kbyte mb9bf415npmc - jne2 main: 384 kbyte work: 32 kbyte 24 kbyte mb9bf 4 1 6npmc - jne2 main: 512 kbyte work: 32 kbyte 32 kbyte mb9bf 4 1 2rpmc - jne2 main: 128 kbyte work: 32 kbyte 8 kbyte plastic ? lqfp 1 20 - pin (0. 5 mm pitch) , ( fpt - 1 20p - m37 ) mb9bf 4 1 4rpmc - jne2 main: 256 kbyte work: 32 kbyte 16 kbyte mb9bf415rpmc - jne2 main: 384 kbyte work: 32 kbyte 24 kbyte mb9bf 4 1 6rpmc - jne2 main: 512 kbyte work: 32 kbyte 32 kbyte mb9bf412nbgl - ge1 main: 128 kbyte work: 32 kbyte 8 kbyte plastic ? pfbga 1 12 - pin (0. 8 mm pitch) , ( bga - 1 12p - m04 ) mb9bf414nbgl - ge1 main: 256 kbyte work: 32 kbyte 16 kbyte mb9bf415nbgl - ge1 main: 384 kbyte work: 32 kbyte 24 kbyte mb9bf416nbgl - ge1 main: 512 kbyte work: 32 kbyte 32 kbyte datasheet 112 MB9B410R-ds706-00026-3v0-e, february 27, 2015 confidential ? package dimensions 100-pin plastic lqfp lead pitch 0.50 mm package width package length 14.00 mm 14.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.65 g 100-pin plastic lqfp (fpt-100p-m23) (fpt-100p-m23) c 2009-2010 fujitsu semiconductor limited f100034s-c-3-4 16.000.20(.630.008)sq 125 51 76 75 100 0.50(.020) 0.220.05 m 0.08(.003) *14.000.10(.551.004)sq 26 50 0.1450.055 (.006.002) 0.08(.003) "a" index 0~8 0.500.20 0.100.10 (stand off) + .008 +0.20 (mounting height) -0.10 1.50 .059 -.004 ( ) 0.600.15 0.25(.010) dimensions in mm (inches). note:the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. details of "a" part (.004.004) (.009.002) (.020.008) (.024.006) datasheet february 27, 2015, MB9B410R-ds706-00026-3v0-e 113 confidential 120-pin plastic lqfp lead pitch 0.50 mm package width package length 16.0 mm 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.88 g code (reference) p-lfqfp120-16 16-0.50 120-pin plastic lqfp (fpt-120p-m37) (fpt-120p-m37) c 2010 fujitsu semiconductor limited f120037sc(1)-1-1 16.00 0.10(.630 .004) sq 18.00 0.20(.709 .008) sq 1 30 31 61 91 60 90 120 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) ( ) 0.08(.003) "a" index .059 ?.004 +.008 ?0.10 +0.20 1.50 (mounting height) 0 ? ~8 ? (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.05 (.004 .002) details of "a" part (stand off) * lead no. ?0.03 +0.05 0.145 ?.001 +.002 .006 dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. datasheet 114 MB9B410R-ds706-00026-3v0-e, february 27, 2015 confidential 100-pin plastic qfp lead pitch 0.65 mm package width package length 14.00 mm 20.00 mm lead shape gullwing sealing method plastic mold mounting height 3.35 mm max code (reference) p-qfp100-14 20-0.65 100-pin plastic qfp (fpt-100p-m36) (fpt-100p-m36) 2011 fujitsu semiconductor limited hmbf100-36sc-1-1 c 130 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) (.551.008) 17.90 0.40 (.705.016) index 0.65(.026) 0.32 0.05 (.013.002) m 0.13(.005) "a" 0.17 0.06 (.007 . 002) 0.10(.004) details of "a" part (.035 . 006) 0.88 0.15 (.031 . 008) 0.80 0.20 0.25(.010) 3.00 +0.35 ?0.20 +.014 ?.008 .118 (mounting height) 0.25 0.20 (.010 . 008) (stand off) 0~8 * *14.000.20 dimensions in mm (inches). note: the valuesin parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. datasheet february 27, 2015, MB9B410R-ds706-00026-3v0-e 115 confidential 112-ball plastic pfbga ball pitch 0.80 mm package width package length 10.00 10.00 mm lead shape soldering ball sealing method plastic mold ball size 0.45 mm mounting height 1.45 mm max. weight 0.22 g 112-ball plastic pfbga (bga-112p-m04) (bga-112p-m04) c 2003-2010 fujitsu semiconductor limited b112004s-c-2-3 10.000.10(.394.004) (.049.008) 1.250.20 (seated height) 6 f index (index area) 10.000.10 (.394.004) (112- 0.18.004) 112- 0.45010 0.350.10 (.014.004) (stand off) 0.10(.004) s b a g h j k ledcba 7 8 9 10 11 5 4 3 2 1 0.80(.031) ref ref 0.80(.031) 0.08(.003) b a s m 0.20(.008) s b s a s 0.20(.008) dimensions in mm (inches). note: the values in parentheses are reference values. d a t a s h e e t 116 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential ? m ajor c hanges page section change results revision 1.0 - - initial release revision 2.0 5 ? features ? external interrupt controller unit corrected the external interrupt input pin . 101 ? electrical characteristics 5. 12 - bit a/d converter ? electrical c haracteristics for the a/d c onverter corrected the value of "compare clock cycle". max: 10000 2000 106 ? ordering information corrected the part number. revision 2.1 - - company name and layout design change revi sion 3.0 2 ? f eatures ? external bus interface added the description of maximum area size 9 ? p ackages deleted the description of es 27, 28 ? l ist of p in f unctions list of pin numbers modified i/o circuit type of p63 to p68 4 7 , 49 ? i/o c ircuit t ype added the description of i 2 c to the type of e, f and i 4 7 , 4 8 ? i/o c ircuit t ype added about +b input 5 4 ? h andling d evices added " tabilizing power supply voltage" 5 4 ? h andling d evices ? c rystal oscillator circuit added the following description "evaluate osc illation of your using crystal oscillator by your mount board." 5 5 ? h andling d evices ? c pin changed the description 5 6 ? b lock d iagram modified the block diagram 5 7 ? m emory m ap memory map(1) modified the area of "extarnal device area" 58 , 59 ? m emory m ap memory map(2)(3) added the summary of flash memory sector and the note 6 6 , 6 7 ? e lectrical c haracteristics 1. absolute maximum ratings added the clamp maximum current added the output current of p80 and p81 added about +b input 6 8 ? electrical c haracteristics 2. recommended operation conditions modified the minimum value of analog reference voltage added smoothing capacitor added the note about less than the minimum power supply voltage 69, 70 ? electrical characteristics 3. dc characterist ics (1) current rating changed the table format added main timer mode current added flash memory current moved a/d converter current modified the unit of low voltage detection circuit (lvd) power supply current 7 3 ? electrical characteristics 4. ac characteristics (1) main clock input characteristics added master clock at ingernal operating clock frequency 7 4 ? electrical characteristics 4. ac characteristics (3) built - in cr oscillation characteristics added frequency stability time at built - in hi gh - speed cr 7 5 ? electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main pll (4 - 2) operating conditions of main pll added main pll clock frequency added the figure of main pll connection 7 6 ? electrical characteristics 4. ac characteristics (6) power - on reset timing added time until releasing power - on reset changed the figure of timing 7 8 - 8 0 ? electrical characteristics 4. ac characteristics (7) external bus timing modified data output time 8 8 - 9 5 ? electrical characterist ics 4. ac characteristics (8) csio/uart timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 10 2 ? electrical characteristics 5. 12bi t a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage modified stage transition time to operation permission modified the minimum value of reference volt age d a t a s h e e t march 11, 2015 , MB9B410R - ds706 - 00026 - 3v0 - e 117 confidential page section change results 105 ? electrical characteristics 7. low - voltage detection characteristics (2) interrupt of low - voltage detection modified lvd stabilization wait time 106 ? electrical characteristics 8. workflash memory write/erase characteristics (1) write / erase tim e modified sector erase time modified half word(16 - bit) write time 107 - 1 10 ? electrical characteristics 9. return time from low - power consumption mode added return time from low - power consumption mode 11 1 ? o rdering i nformation change to full part numb er 112 - 1 15 ? p ackage d imensions deleted fpt - 100p - m20 and fpt - 120p - m21 d a t a s h e e t 118 MB9B410R - ds706 - 00026 - 3v0 - e, march 11, 2015 confidential colop hon the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, develope d and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injur y, severe physical damage or o ther loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices hav e an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and othe r abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may c ontain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non - infringement of third - party rights, or any other warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising o ut of the use of the information in this document. copyright ? 201 2 - 201 5 spansion all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse tm , ornand tm , easy designsim tm , traveo tm and combinations thereof, are trademarks and regis tered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners. |
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